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Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
MC68HC908GZ8
Data Sheet
M68HC08
Microcontrollers
MC68HC908GZ8/D Rev. 0 2/2003
MOTOROLA.COM/SEMICONDUCTORS
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC68HC908GZ8
Data Sheet
Freescale Semiconductor, Inc...
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://motorola.com/semiconductors The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
Motorola and the Stylized M Logo are registered trademarks of Motorola, Inc. DigitalDNA is a trademark of Motorola, Inc. This product incorporates SuperFlash(R) technology licensed from SST. MC68HC908GZ8 MOTOROLA
(c) Motorola, Inc., 2003 Data Sheet 3
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Freescale Semiconductor, Inc.
Revision History Revision History
Date February, 2003 Revision Level N/A Initial release Description Page Number(s) N/A
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Data Sheet 4 Revision History
MC68HC908GZ8 MOTOROLA
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Freescale Semiconductor, Inc.
Data Sheet -- MC68HC908GZ8
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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Section 3. Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Section 4. Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Section 5. Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . 65 Section 6. Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Section 7. Clock Generator Module (CGM). . . . . . . . . . . . . . . . . . . . . . 83 Section 8. Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . 103 Section 9. Computer Operating Properly (COP) Module. . . . . . . . . . 107 Section 10. Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . 111 Section 11. FLASH Memory (FLASH) . . . . . . . . . . . . . . . . . . . . . . . . . 125 Section 12. External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Section 13. Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . 139 Section 14. Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . . . . . . . . . . . . . 145 Section 15. Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Section 16. MSCAN08 Controller (MSCAN08) . . . . . . . . . . . . . . . . . . 161 Section 17. Input/Output (I/O) Ports . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Section 18. Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . 217 Section 19. Enhanced Serial Communications Interface (ESCI) Module . . . . . . . . . . . . . . . . . . . . . . . . . 219 Section 20. System Integration Module (SIM) . . . . . . . . . . . . . . . . . . 255
MC68HC908GZ8 MOTOROLA List of Sections
Data Sheet 5
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Freescale Semiconductor, Inc.
List of Sections
Section 21. Serial Peripheral Interface (SPI) Module. . . . . . . . . . . . . 275 Section 22. Timebase Module (TBM). . . . . . . . . . . . . . . . . . . . . . . . . . 299 Section 23. Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . 305 Section 24. Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . 323 Section 25. Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . . 339
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Data Sheet 6 List of Sections
MC68HC908GZ8 MOTOROLA
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Freescale Semiconductor, Inc.
Data Sheet -- MC68HC908GZ8
Table of Contents
Section 1. General Description
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Standard Features of the MC68HC908GZ8 . . . . . . . . . . . . . . . . . . . 21 Features of the CPU08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 26 26 26 26 27 27 27 27 27 27 28 28 28 1.2 1.2.1 1.2.2 1.3 1.4 1.5 1.5.1 1.5.2 1.5.3 1.5.4 1.5.5 1.5.6 1.5.7
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Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Supply Pins (VDD and VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CGM Power Supply Pins (VDDA and VSSA) . . . . . . . . . . . . . . . . . . . External Filter Capacitor Pin (VCGMXFC). . . . . . . . . . . . . . . . . . . . . . ADC Power Supply/Reference Pins (VDDAD/VREFH and VSSAD/VREFL) . . . . . . . . . . . . . . . . . . . . . . . . 1.5.8 Port A Input/Output (I/O) Pins (PTA7/KBD7-PTA0/KBD0). . . . . . . . 1.5.9 Port B I/O Pins (PTB7/AD7-PTB0/AD0). . . . . . . . . . . . . . . . . . . . . . 1.5.10 Port C I/O Pins (PTC6-PTC0/CANTX). . . . . . . . . . . . . . . . . . . . . . . 1.5.11 Port D I/O Pins (PTD7/T2CH1-PTD0/SS) . . . . . . . . . . . . . . . . . . . . 1.5.12 Port E I/O Pins (PTE5-PTE2, PTE1/RxD, and PTE0/TxD) . . . . . . .
Section 2. Memory Map
2.1 2.2 2.3 2.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Section 3. Low-Power Modes
3.1 3.1.1 3.1.2 3.2 3.2.1 3.2.2
MC68HC908GZ8 MOTOROLA Table of Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Data Sheet 7
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Freescale Semiconductor, Inc.
Table of Contents
3.3 3.3.1 3.3.2 3.4 3.4.1 3.4.2 3.5 3.5.1 3.5.2 3.6 3.6.1 3.6.2 3.7 3.7.1 3.7.2 3.8 3.8.1 3.8.2 3.9 3.9.1 3.9.2 Break Module (BRK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Clock Generator Module (CGM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Computer Operating Properly Module (COP). . . . . . . . . . . . . . . . . . . . . 42 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 External Interrupt Module (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Low-Voltage Inhibit Module (LVI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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3.10 Motorola Scalable Controller Area Network Module (MSCAN) . . . . . . . 44 3.10.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.10.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.11 Enhanced Serial Communications Interface Module (ESCI) . . . . . . . . . 45 3.11.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.11.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.12 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . . 45 3.12.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.12.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.13 Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.13.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.13.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.14 Timer Interface Module (TIM1 and TIM2) . . . . . . . . . . . . . . . . . . . . . . . . 46 3.14.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.14.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.15 3.16 Exiting Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Exiting Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Data Sheet 8 Table of Contents
MC68HC908GZ8 MOTOROLA
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Freescale Semiconductor, Inc.
Table of Contents
Section 4. Resets and Interrupts
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 49 49 49 49 50 50 51 51 51 51 53 53 54 57 57 57 57 57 57 58 58 59 59 59 60 61 62 62 63 4.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 Effects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . 4.2.3.3 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3.4 Illegal Opcode Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3.5 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.4 System Integration Module (SIM) Reset Status Register . . . . . . . . . 4.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 Effects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2.1 Software Interrupt (SWI) Instruction . . . . . . . . . . . . . . . . . . . . . . . 4.3.2.2 Break Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2.3 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2.4 Clock Generator (CGM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2.5 Timer Interface Module 1 (TIM1). . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2.6 Timer Interface Module 2 (TIM2). . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2.7 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2.8 Serial Communications Interface (SCI) . . . . . . . . . . . . . . . . . . . . . 4.3.2.9 KBD0-KBD7 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2.10 Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2.11 Timebase Module (TBM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2.12 Motorola Scalable Controller Area Network Module (MSCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3.2 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.3.3 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Section 5. Analog-to-Digital Converter (ADC)
5.1 5.2 5.3 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Port I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conversion Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Result Justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 65 66 67 67 67 67
Monotonicity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
MC68HC908GZ8 MOTOROLA Table of Contents
Data Sheet 9
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Table of Contents
5.5 5.6 5.6.1 5.6.2 5.7 5.7.1 5.7.2 5.7.3 5.7.4 5.7.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Analog Power Pin (VDDAD). . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Analog Ground Pin (VSSAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Voltage Reference High Pin (VREFH) . . . . . . . . . . . . . . . . . . . . ADC Voltage Reference Low Pin (VREFL) . . . . . . . . . . . . . . . . . . . . ADC Voltage In (VADIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 69 70 70 70 70 71 71 73 73 73 74 74 75
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5.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.1 ADC Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.2 ADC Data Register High and Data Register Low . . . . . . . . . . . . . . . 5.8.2.1 Left Justified Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.2.2 Right Justified Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.2.3 Left Justified Signed Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.2.4 Eight Bit Truncation Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.3 ADC Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 6. Break Module (BRK)
6.1 6.2 6.3 6.3.1 6.3.2 6.3.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flag Protection During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Break Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 79 79 79 80 80 81 81 82
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Section 7. Clock Generator Module (CGM)
7.1 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6
Data Sheet 10 Table of Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase-Locked Loop Circuit (PLL). . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Acquisition and Tracking Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . Manual and Automatic PLL Bandwidth Modes . . . . . . . . . . . . . . . . . Programming the PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 85 85 85 86 86 88
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7.3.7 7.3.8 7.3.9
Special Programming Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 92 92 92 92 92 92 92 92 93 93 93 93 94 96 97 98 98
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7.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.1 Crystal Amplifier Input Pin (OSC1) . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . . . . . . . . 7.4.3 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . . . . . . . 7.4.4 PLL Analog Power Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.5 PLL Analog Ground Pin (VSSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.6 Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . . . . . . . . . 7.4.7 Oscillator Stop Mode Enable Bit (OSCSTOPENB). . . . . . . . . . . . . . 7.4.8 Crystal Output Frequency Signal (CGMXCLK). . . . . . . . . . . . . . . . . 7.4.9 CGM Base Clock Output (CGMOUT) . . . . . . . . . . . . . . . . . . . . . . . . 7.4.10 CGM CPU Interrupt (CGMINT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.6 7.7 7.7.1 7.7.2 7.7.3 7.8 7.8.1 7.8.2 7.8.3 CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Multiplier Select Register High . . . . . . . . . . . . . . . . . . . . . . . . . PLL Multiplier Select Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . PLL VCO Range Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . Parametric Influences on Reaction Time . . . . . . . . . . . . . . . . . . . . Choosing a Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 100 101 102
Section 8. Configuration Register (CONFIG)
8.1 8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Section 9. Computer Operating Properly (COP) Module
9.1 9.2 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 108 108 108 108 109
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9.3.6 9.3.7 9.3.8 9.4 9.5 9.6 9.7 9.7.1 9.7.2 9.8 Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 COPD (COP Disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
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Section 10. Central Processor Unit (CPU)
10.1 10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 112 112 113 113 114 114
10.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.2 Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.5 Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
10.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 10.5.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 10.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 10.6 10.7 10.8 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Section 11. FLASH Memory (FLASH)
11.1 11.2 11.3 11.4 11.5 11.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 FLASH Program/Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
11.7 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 11.7.1 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 11.8 11.9 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Data Sheet 12 Table of Contents
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Section 12. External Interrupt (IRQ)
12.1 12.2 12.3 12.4 12.5 12.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 137 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Section 13. Keyboard Interrupt Module (KBI)
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13.1 13.2 13.3 13.4
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
13.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 13.5.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 13.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 13.6 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . 142 13.7 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 13.7.1 Keyboard Status and Control Register . . . . . . . . . . . . . . . . . . . . . . 143 13.7.2 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . 144
Section 14. Low-Voltage Inhibit (LVI)
14.1 14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 145 147 147 147 147
14.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.1 Polled LVI Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.2 Forced Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.3 Voltage Hysteresis Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.4 LVI Trip Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4 14.5
LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
14.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 14.6.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 14.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Section 15. Monitor ROM (MON)
15.1 15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
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15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.1 Normal Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.2 Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.3 Monitor Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.4 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.5 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.6 Baud Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3.7 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.4 149 154 154 154 155 155 155 156
Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Section 16. MSCAN08 Controller (MSCAN08)
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16.1 16.2 16.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 External Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 163 163 163 165
16.4 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.4.1 Background. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.4.2 Receive Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.4.3 Transmit Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5
Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
16.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 16.6.1 Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 16.6.2 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 16.7 Protocol Violation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 172 172 174 174 174 174 16.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.8.1 MSCAN08 Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.8.2 MSCAN08 Soft Reset Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.8.3 MSCAN08 Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.8.4 CPU Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.8.5 Programmable Wakeup Function . . . . . . . . . . . . . . . . . . . . . . . . . . 16.9
Timer Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
16.10 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 16.11 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 16.12 Programmer's Model of Message Storage . . . . . . . . . . . . . . . . . . . . . . 16.12.1 Message Buffer Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.12.2 Identifier Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.12.3 Data Length Register (DLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.12.4 Data Segment Registers (DSRn) . . . . . . . . . . . . . . . . . . . . . . . . . . 16.12.5 Transmit Buffer Priority Registers. . . . . . . . . . . . . . . . . . . . . . . . . . 16.13 Programmer's Model of Control Registers . . . . . . . . . . . . . . . . . . . . . . 16.13.1 MSCAN08 Module Control Register 0 . . . . . . . . . . . . . . . . . . . . . . 16.13.2 MSCAN08 Module Control Register 1 . . . . . . . . . . . . . . . . . . . . . . 16.13.3 MSCAN08 Bus Timing Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . 179 180 181 182 182 183 183 185 186 187
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Table of Contents
16.13.4 16.13.5 16.13.6 16.13.7 16.13.8 16.13.9 16.13.10 16.13.11 16.13.12 16.13.13
MSCAN08 Bus Timing Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . MSCAN08 Receiver Flag Register (CRFLG) . . . . . . . . . . . . . . . . . MSCAN08 Receiver Interrupt Enable Register . . . . . . . . . . . . . . . MSCAN08 Transmitter Flag Register . . . . . . . . . . . . . . . . . . . . . . . MSCAN08 Transmitter Control Register. . . . . . . . . . . . . . . . . . . . . MSCAN08 Identifier Acceptance Control Register . . . . . . . . . . . . . MSCAN08 Receive Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . MSCAN08 Transmit Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . MSCAN08 Identifier Acceptance Registers . . . . . . . . . . . . . . . . . . MSCAN08 Identifier Mask Registers (CIDMR0-CIDMR3) . . . . . . .
188 189 191 192 193 194 195 195 196 197
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Section 17. Input/Output (I/O) Ports
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 202 202 202 204 17.2 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.2.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.2.2 Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.2.3 Port A Input Pullup Enable Register . . . . . . . . . . . . . . . . . . . . . . . .
17.3 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 17.3.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 17.3.2 Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 17.4 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.4.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.4.2 Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.4.3 Port C Input Pullup Enable Register . . . . . . . . . . . . . . . . . . . . . . . . 17.5 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.1 Port D Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.2 Data Direction Register D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.3 Port D Input Pullup Enable Register . . . . . . . . . . . . . . . . . . . . . . . . 207 207 208 209 210 210 211 213
17.6 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 17.6.1 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 17.6.2 Data Direction Register E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Section 18. Random-Access Memory (RAM)
18.1 18.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Section 19. Enhanced Serial Communications Interface (ESCI) Module
19.1 19.2 19.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 19.4.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
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19.4.2 19.4.2.1 19.4.2.2 19.4.2.3 19.4.2.4 19.4.2.5 19.4.2.6 19.4.3 19.4.3.1 19.4.3.2 19.4.3.3 19.4.3.4 19.4.3.5 19.4.3.6 19.4.3.7 19.4.3.8 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Idle Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inversion of Transmitted Output . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sampling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 223 223 225 226 226 226 226 228 228 228 230 230 232 233 233
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19.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 19.5.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 19.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 19.6 ESCI During Break Module Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 234 19.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 19.7.1 PTE0/TxD (Transmit Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 19.7.2 PTE1/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 19.8 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.8.1 ESCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.8.2 ESCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.8.3 ESCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.8.4 ESCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.8.5 ESCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.8.6 ESCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.8.7 ESCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.8.8 ESCI Prescaler Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.9 ESCI Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.9.1 ESCI Arbiter Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.9.2 ESCI Arbiter Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.9.3 Bit Time Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.9.4 Arbitration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 235 237 239 240 243 244 244 246 250 250 251 251 253
Section 20. System Integration Module (SIM)
20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 257 257 257 258 20.2 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . 20.2.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.2.2 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . . . . . . . 20.2.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . . . . . .
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20.3 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.3.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.3.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . 20.3.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.3.2.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . 20.3.2.3 Illegal Opcode Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.3.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.3.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . 20.3.2.6 Monitor Mode Entry Module Reset (MODRST). . . . . . . . . . . . . . 20.4 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.4.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . 20.4.2 SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . . . . . . . 20.4.3 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.5 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.5.1 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.5.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.5.1.2 SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.5.1.3 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.5.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.5.3 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.5.4 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . .
258 259 259 260 261 261 261 262 262 262 262 262 262 263 263 265 266 266 268 268 268
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20.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 20.6.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 20.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 20.7 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.7.1 Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.7.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.7.3 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 271 272 273
Section 21. Serial Peripheral Interface (SPI) Module
21.1 21.2 21.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
21.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 21.4.1 Master Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 21.4.2 Slave Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 21.5 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.5.1 Clock Phase and Polarity Controls . . . . . . . . . . . . . . . . . . . . . . . . . 21.5.2 Transmission Format When CPHA = 0. . . . . . . . . . . . . . . . . . . . . . 21.5.3 Transmission Format When CPHA = 1. . . . . . . . . . . . . . . . . . . . . . 21.5.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.6 279 279 280 281 282
Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
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21.7 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 21.7.1 Overflow Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 21.7.2 Mode Fault Error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 21.8 21.9 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
21.10 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 21.10.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 21.10.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 21.11 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 21.12 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.12.1 MISO (Master In/Slave Out) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.12.2 MOSI (Master Out/Slave In) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.12.3 SPSCK (Serial Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.12.4 SS (Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.12.5 CGND (Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.13 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.13.1 SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.13.2 SPI Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . 21.13.3 SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 291 291 291 291 293 293 293 294 297
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Section 22. Timebase Module (TBM)
22.1 22.2 22.3 22.4 22.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 TBM Interrupt Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
22.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 22.6.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 22.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 22.7 Timebase Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
Section 23. Timer Interface Module (TIM)
23.1 23.2 23.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 306 309 309 309 309 310
23.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.4.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.4.3.1 Unbuffered Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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23.4.4 23.4.4.1 23.4.4.2 23.4.4.3 23.5
Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . Unbuffered PWM Signal Generation. . . . . . . . . . . . . . . . . . . . . . Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
310 311 312 312
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
23.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 23.6.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 23.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 23.7 23.8 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 315 315 317 317 318 321
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23.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.9.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 23.9.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.9.3 TIM Counter Modulo Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23.9.4 TIM Channel Status and Control Registers . . . . . . . . . . . . . . . . . . 23.9.5 TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 24. Electrical Specifications
24.1 24.2 24.3 24.4 24.5 24.6 24.7 24.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 5-Vdc Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 3.3-Vdc Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 5.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
24.9 Clock Generation Module Characteristics . . . . . . . . . . . . . . . . . . . . . . 330 24.9.1 CGM Component Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . 330 24.9.2 CGM Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 24.10 5.0-Volt ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 24.11 3.3-Volt ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 24.12 5.0-Volt SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 24.13 3.3-Volt SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 24.14 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 337 24.15 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
MC68HC908GZ8 MOTOROLA Table of Contents
Data Sheet 19
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Table of Contents
Section 25. Ordering Information and Mechanical Specifications
25.1 25.2 25.3 25.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 32-Pin Low-Profile Quad Flat Pack (LQFP) . . . . . . . . . . . . . . . . . . . . . 340 48-Pin Low-Profile Quad Flat Pack (LQFP) . . . . . . . . . . . . . . . . . . . . . 341
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Data Sheet 20 Table of Contents
MC68HC908GZ8 MOTOROLA
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Data Sheet -- MC68HC908GZ8
Section 1. General Description
1.1 Introduction
The MC68HC908GZ8 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types.
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1.2 Features
For convenience, features have been organized to reflect: * Standard features of the MC68HC908GZ8 * Features of the CPU08 1.2.1 Standard Features of the MC68HC908GZ8 Features of the MC68HC908GZ8 include: * High-performance M68HC08 architecture optimized for C-compilers * Fully upward-compatible object code with M6805, M146805, and M68HC05 Families * 8-MHz internal bus frequency * Clock generation module supporting 1-MHz to 8-MHz crystals * MSCAN08 (Motorola scalable controller area network) controller (implementing 2.0b protocol as defined in BOSCH specification dated September 1991) * FLASH program memory security(1) * On-chip programming firmware for use with host personal computer which does not require high voltage for entry * In-system programming (ISP) * System protection features: - Optional computer operating properly (COP) reset - Low-voltage detection with optional reset and selectable trip points for 3.3-V and 5.0-V operation - Illegal opcode detection with reset - Illegal address detection with reset
1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908GZ8 MOTOROLA General Description Data Sheet 21
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General Description
* * Low-power design; fully static with stop and wait modes Standard low-power modes of operation: - Wait mode - Stop mode Master reset pin and power-on reset (POR) 8 Kbytes of on-chip FLASH memory 1 Kbyte of on-chip random-access memory (RAM) 406 bytes of FLASH programming routines read-only memory (ROM) Serial peripheral interface (SPI) module Enhanced serial communications interface (ESCI) module Fine adjust baud rate prescalers for precise control of baud rate Arbiter module: - Measurement of received bit timings for baud rate recovery without use of external timer - Bitwise arbitration for arbitrated UART communications LIN specific enhanced features: - Generation of LIN 1.2 break symbols without extra software steps on each message - Break detection filtering to prevent false interrupts Two 16-bit, 2-channel timer interface modules (TIM1 and TIM2) with selectable input capture, output compare, and pulse-width modulation (PWM) capability on each channel 8-channel, 10-bit successive approximation analog-to-digital converter (ADC) BREAK (BRK) module to allow single breakpoint setting during in-circuit debugging Internal pullups on IRQ and RST to reduce customer system cost Up to 37 general-purpose input/output (I/O) pins, including: - 28 shared-function I/O pins - Up to nine dedicated I/O pins, depending on package choice Selectable pullups on inputs only on ports A, C, and D. Selection is on an individual port bit basis. During output mode, pullups are disengaged. High current 10-mA sink/source capability on all port pins Higher current 20-mA sink/source capability on PTC0-PTC4 Timebase module (TBM) with clock prescaler circuitry for eight user selectable periodic real-time interrupts with optional active clock source during stop mode for periodic wakeup from stop using an external crystal User selection of having the oscillator enabled or disabled during stop mode 8-bit keyboard wakeup port 2 mA maximum current injection on all port pins to maintain input protection
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* * * * * * * *
*
*
* * * *
* * * *
* * *
Data Sheet 22 General Description
MC68HC908GZ8 MOTOROLA
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General Description MCU Block Diagram
*
*
*
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Available packages: - 32-pin quad flat pack (LQFP) - 48-pin quad flat pack (LQFP) Specific features of the MC68HC908GZ8 in 32-pin LQFP are: - Port A is only 4 bits: PTA0-PTA3; 4-pin keyboard interrupt (KBI) module - Port B is only 6 bits: PTB0-PTB5; 6-channel ADC module - Port C is only 2 bits: PTC0-PTC1; shared with MSCAN08 module - Port D is only 7 bits: PTD0-PTD6; shared with SPI, TIM1, and TIM2 modules - Port E is only 2 bits: PTE0-PTE1; shared with ESCI module Specific features of the MC68HC908GZ8 in 48-pin LQFP are: - Port A is 8 bits: PTA0-PTA7; 8-pin KBI module - Port B is 8 bits: PTB0-PTB7; 8-channel ADC module - Port C is only 7 bits: PTC0-PTC6; shared with MSCAN08 module - Port D is 8 bits: PTD0-PTD7; shared with SPI, TIM1, and TIM2 modules - Port E is only 6 bits: PTE0-PTE5; shared with ESCI module
1.2.2 Features of the CPU08 Features of the CPU08 include: * Enhanced HC05 programming model * Extensive loop control functions * 16 addressing modes (eight more than the HC05) * 16-bit index register and stack pointer * Memory-to-memory data transfers * Fast 8 x 8 multiply instruction * Fast 16/8 divide instruction * Binary-coded decimal (BCD) instructions * Optimization for controller applications * Efficient C language support
1.3 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC908GZ8.
1.4 Pin Assignments
Figure 1-2 and Figure 1-3 illustrate the pin assignments for the 32-pin LQFP and 48-pin LQFP respectively.
MC68HC908GZ8 MOTOROLA General Description
Data Sheet 23
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INTERNAL BUS M68HC08 CPU DDRA ARITHMETIC/LOGIC UNIT (ALU) SINGLE BREAKPOINT BREAK MODULE DDRB DUAL VOLTAGE LOW-VOLTAGE INHIBIT MODULE 8-BIT KEYBOARD INTERRUPT MODULE 2-CHANNEL TIMER INTERFACE MODULE 1 DDRC 2-CHANNEL TIMER INTERFACE MODULE 2 PORTC PORTB PROGRAMMABLE TIMEBASE MODULE PORTA PTA7/KBD7-PTA0/KBD0(1)
General Description
DDRD
DDRE
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CLOCK GENERATOR MODULE 1-8 MHz OSCILLATOR PHASE LOCKED LOOP COMPUTER OPERATING PROPERLY MODULE SERIAL PERIPHERAL INTERFACE MODULE MONITOR MODULE DATA BUS SWITCH MODULE MEMORY MAP MODULE PORTE ENHANCED SERIAL COMUNICATIONS INTERFACE MODULE SYSTEM INTEGRATION MODULE SINGLE EXTERNAL INTERRUPT MODULE 10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE POWER-ON RESET MODULE PORTD POWER CONFIGURATION REGISTER 1-2 MODULE MSCAN08 MODULE
24
USER RAM -- 1024 BYTES PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4 PTB3/AD3 PTB2/AD2 PTB1/AD1 PTB0/AD0 PTC6(1) PTC5(1) PTC4(1), (2) PTC3(1), (2) PTC2(1), (2) PTC1/CANRX(1), (2) PTC0/CANTX(1), (2) PTD7/T2CH1(1) PTD6/T2CH0(1) PTD5/T1CH1(1) PTD4/T1CH0(1) PTD3/SPSCK(1) PTD2/MOSI(1) PTD1/MISO(1) PTD0/SS(1) PTE5-PTE2 PTE1/RxD PTE0/TxD SECURITY MODULE MONITOR MODE ENTRY MODULE
Data Sheet
CPU REGISTERS
CONTROL AND STATUS REGISTERS -- 64 BYTES
USER FLASH -- 7936 BYTES
MONITOR ROM -- 350 BYTES
FLASH PROGRAMMING ROUTINES ROM -- 406 BYTES
USER FLASH VECTOR SPACE -- 44 BYTES
OSC1 OSC2
General Description
CGMXFC
RST(3)
IRQ(3)
VDDAD/VREFH
VDDAD/VREFL
VDD VSS VDDA VSSA
1. Ports are software configurable with pullup device if input port. 2. Higher current drive port pins 3. Pin contains integrated pullup device
MC68HC908GZ8
MOTOROLA
Figure 1-1. MCU Block Diagram
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General Description Pin Assignments
PTC1/CANRX
PTC0/CANTX
26
32 OSC1
31
30
29
28
27
RST PTE0/TxD PTE1/RxD IRQ PTD0/SS PTD1/MISO
1 2 3 4 5 6 7 8
25
PTA3/KBD3
24 23 22 21 20 19 18
CGMXFC
OSC2
VDDA
VSSA
PTA2/KBD2 PTA1/KBD1 PTA0/KBD0 VSSAD/VREFL VDDAD/VREFH PTB5/AD5 PTB4/AD4 PTB3/AD3
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PTD2/MOSI PTD3/SPSCK
10
11
12
13
14
PTD4/T1CH0
PTD5/T1CH1
PTD6/T2CH0
PTB0/AD0
PTB1/AD1 PTA6/KBD6
VSS
VDD
15
9
Figure 1-2. 32-Pin LQFP Pin Assignments
PTC1/CANRX PTC0/CANTX
37 PTA3/KBD3 36 PTA2/KBD2 35 34 33 32 31 30 29 28 27 26 14 18 19 20 21 15 16 17 22 23
PTA7/KBD7
PTA5/KBD5
39
PTB2/AD2
38
16
17
48 OSC1
46
45
44
47
43
42
41
RST 1 PTE0/TxD PTE1/RxD PTE2 PTE3 PTE4 PTE5 IRQ PTD0/SS PTD1/MISO PTD2/MOSI PTD3/SPSCK 12 VSS 13
2 3 4 5 6 7 8 9 10 11
40
PTA4/KBD4
CGMXFC
OSC2
VDDA
VSSA
PTA1/KBD1 PTA0/KBD0 PTC6 PTC5 VSSAD/VREFL VDDAD/VREFH PTB7/AD7 PTB6/AD6 PTB5/AD5 PTB4/AD4
25 PTB3/AD3
PTD5/T1CH1
PTD6/T2CH0
PTD7/T2CH1
Figure 1-3. 48-Pin LQFP Pin Assignments
MC68HC908GZ8 MOTOROLA General Description Data Sheet 25
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PTD4/T1CH0
PTB2/AD2 24
PTB0/AD0
PTB1/AD1
VDD
PTC2
PTC3
PTC4
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General Description
1.5 Pin Functions
Descriptions of the pin functions are provided here. 1.5.1 Power Supply Pins (VDD and VSS) VDD and VSS are the power supply and ground pins. The MCU operates from a single power supply. Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU as Figure 1-4 shows. Place the C1 bypass capacitor as close to the MCU as possible. Use a high-frequency-response ceramic capacitor for C1. C2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels.
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MCU VDD VSS
C1 0.1 F
+ C2
VDD Note: Component values shown represent typical applications.
Figure 1-4. Power Supply Bypassing 1.5.2 Oscillator Pins (OSC1 and OSC2) OSC1 and OSC2 are the connections for an external crystal, resonator, or clock circuit. See Section 7. Clock Generator Module (CGM). 1.5.3 External Reset Pin (RST) A logic 0 on the RST pin forces the MCU to a known startup state. RST is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. This pin contains an internal pullup resistor. See Section 20. System Integration Module (SIM).
Data Sheet 26 General Description
MC68HC908GZ8 MOTOROLA
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General Description Pin Functions
1.5.4 External Interrupt Pin (IRQ) IRQ is an asynchronous external interrupt pin. This pin contains an internal pullup resistor. See Section 12. External Interrupt (IRQ). 1.5.5 CGM Power Supply Pins (VDDA and VSSA) VDDA and VSSA are the power supply pins for the analog portion of the clock generator module (CGM). Decoupling of these pins should be as per the digital supply. See Section 7. Clock Generator Module (CGM). 1.5.6 External Filter Capacitor Pin (VCGMXFC)
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CGMXFC is an external filter capacitor connection for the CGM. See Section 7. Clock Generator Module (CGM). 1.5.7 ADC Power Supply/Reference Pins (VDDAD/VREFH and VSSAD/VREFL) VDDAD and VSSAD are the power supply pins to the analog-to-digital converter (ADC). VREFH and VREFL are the reference voltage pins for the ADC. VREFH is the high reference supply for the ADC, and by default the VDDAD/VREFH pin should be externally filtered and connected to the same voltage potential as VDD. VREFL is the low reference supply for the ADC, and by default the VSSAD/VREFL pin should be connected to the same voltage potential as VSS. See Section 5. Analog-to-Digital Converter (ADC). 1.5.8 Port A Input/Output (I/O) Pins (PTA7/KBD7-PTA0/KBD0) PTA7-PTA0 are general-purpose, bidirectional I/O port pins. Any or all of the port A pins can be programmed to serve as keyboard interrupt pins. PTA7-PTA4 are only available on the 48-pin LQFP package. See Section 17. Input/Output (I/O) Ports and Section 13. Keyboard Interrupt Module (KBI). These port pins also have selectable pullups when configured for input mode. The pullups are disengaged when configured for output mode. The pullups are selectable on an individual port bit basis. 1.5.9 Port B I/O Pins (PTB7/AD7-PTB0/AD0) PTB7-PTB0 are general-purpose, bidirectional I/O port pins that can also be used for analog-to-digital converter (ADC) inputs. PTB7-PTB4 are only available on the 48-pin LQFP package. See Section 17. Input/Output (I/O) Ports and Section 5. Analog-to-Digital Converter (ADC).
MC68HC908GZ8 MOTOROLA General Description
Data Sheet 27
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General Description
1.5.10 Port C I/O Pins (PTC6-PTC0/CANTX) PTC6 and PTC5 are general-purpose, bidirectional I/O port pins. PTC4-PTC0 are general-purpose, bidirectional I/O port pins that contain higher current sink/source capability. PTC6-PTC2 are only available on the 48-pin LQFP package. See Section 17. Input/Output (I/O) Ports. PTC1 and PTC0 can be programmed to be MSCAN08 pins. These port pins also have selectable pullups when configured for input mode. The pullups are disengaged when configured for output mode. The pullups are selectable on an individual port bit basis.
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1.5.11 Port D I/O Pins (PTD7/T2CH1-PTD0/SS) PTD7-PTD0 are special-function, bidirectional I/O port pins. PTD3-PTD0 can be programmed to be serial peripheral interface (SPI) pins, while PTD7-PTD4 can be individually programmed to be timer interface module (TIM1 and TIM2) pins. PTD7 is only available on the 48-pin LQFP package. See Section 23. Timer Interface Module (TIM), Section 21. Serial Peripheral Interface (SPI) Module, and Section 17. Input/Output (I/O) Ports. These port pins also have selectable pullups when configured for input mode. The pullups are disengaged when configured for output mode. The pullups are selectable on an individual port bit basis. 1.5.12 Port E I/O Pins (PTE5-PTE2, PTE1/RxD, and PTE0/TxD) PTE5-PTE0 are general-purpose, bidirectional I/O port pins. PTE1 and PTE0 can also be programmed to be enhanced serial communications interface (ESCI) pins. PTE5-PTE2 are only available on the 48-pin LQFP package. See Section 19. Enhanced Serial Communications Interface (ESCI) Module and Section 17. Input/Output (I/O) Ports. NOTE: Any unused inputs and I/O ports should be tied to an appropriate logic level (either VDD or VSS). Although the I/O ports of the MC68HC908GZ8 do not require termination, termination is recommended to reduce the possibility of static damage.
Data Sheet 28 General Description
MC68HC908GZ8 MOTOROLA
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Data Sheet -- MC68HC908GZ8
Section 2. Memory Map
2.1 Introduction
The CPU08 can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes:
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* * * * *
7680 bytes of user FLASH memory 1024 bytes of random-access memory (RAM) 406 bytes of FLASH programming routines read-only memory (ROM) 44 bytes of user-defined vectors 350 bytes of monitor ROM
2.2 Unimplemented Memory Locations
Accessing an unimplemented location can cause an illegal address reset. In the memory map (Figure 2-1) and in register figures in this document, unimplemented locations are shaded.
2.3 Reserved Memory Locations
Accessing a reserved location can have unpredictable effects on microcontroller (MCU) operation. In the Figure 2-1 and in register figures in this document, reserved locations are marked with the word Reserved or with the letter R.
2.4 Input/Output (I/O) Section
Most of the control, status, and data registers are in the zero page area of $0000-$003F. Additional I/O registers have these addresses: * * * * * * *
MC68HC908GZ8 MOTOROLA Memory Map
$FE00; break status register, BSR $FE01; SIM reset status register, SRSR $FE02; break auxiliary register, BRKAR $FE03; break flag control register, BFCR $FE04; interrupt status register 1, INT1 $FE05; interrupt status register 2, INT2 $FE06; interrupt status register 3, INT3
Data Sheet 29
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Memory Map
* * * * * * * $FE07; reserved $FE08; FLASH control register, FLCR $FE09; break address register high, BRKH $FE0A; break address register low, BRKL $FE0B; break status and control register, BRKSCR $FE0C; LVI status register, LVISR $FF7E; FLASH block protect register, FLBPR
Data registers are shown in Figure 2-2. Table 2-1 is a list of vector locations.
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$0000 $003F $0040 $043F $0440 $04FF $0500 $057F $0580 $1BFF $1C00 $1D95 $1D96 $DFFF $E000 $FDFF $FE00 SIM BREAK STATUS REGISTER (SBSR) FLASH MEMORY 7680 BYTES UNIMPLEMENTED 49,770 BYTES FLASH PROGRAMMING ROUTINES ROM 406 BYTES UNIMPLEMENTED 5760 BYTES MSCAN08 CONTROL AND MESSAGE BUFFER 128 BYTES UNIMPLEMENTED 192 BYTES RAM 1024 BYTES I/O REGISTERS 64 BYTES
Figure 2-1. Memory Map
Data Sheet 30 Memory Map MC68HC908GZ8 MOTOROLA
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Memory Map Input/Output (I/O) Section
$FE01 $FE02 $FE03 $FE04 $FE05 $FE06 $FE07 $FE08
SIM RESET STATUS REGISTER (SRSR) RESERVED SIM BREAK FLAG CONTROL REGISTER (SBFCR) INTERRUPT STATUS REGISTER 1 (INT1) INTERRUPT STATUS REGISTER 2 (INT2) INTERRUPT STATUS REGISTER 3 (INT3) RESERVED FLASH CONTROL REGISTER (FLCR) BREAK ADDRESS REGISTER HIGH (BRKH) BREAK ADDRESS REGISTER LOW (BRKL) BREAK STATUS AND CONTROL REGISTER (BRKSCR) LVI STATUS REGISTER (LVISR) UNIMPLEMENTED 3 BYTES UNIMPLEMENTED 16 BYTES RESERVED FOR COMPATIBILITY WITH MONITOR CODE FOR A-FAMILY PART MONITOR ROM 350 BYTES FLASH BLOCK PROTECT REGISTER (FLBPR) UNIMPLEMENTED 85 BYTES
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$FE09 $FE0A $FE0B $FE0C $FE0D $FE0F $FE10 $FE1F $FE20 $FF7D $FF7E $FF7F $FFD3 $FFD4 $FFFF(1)
FLASH VECTORS 44 BYTES
1. $FFF6-$FFFD used for eight security bytes
Figure 2-1. Memory Map (Continued)
MC68HC908GZ8 MOTOROLA Memory Map
Data Sheet 31
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Memory Map
Addr. $0000
Register Name Port A Data Register Read: (PTA) Write: See page 202. Reset: Port B Data Register Read: (PTB) Write: See page 204. Reset: Port C Data Register Read: (PTC) Write: See page 207. Reset: Port D Data Register Read: (PTD) Write: See page 210. Reset: Data Direction Register A Read: (DDRA) Write: See page 202. Reset: Data Direction Register B Read: (DDRB) Write: See page 205. Reset: Data Direction Register C Read: (DDRC) Write: See page 208. Reset: Data Direction Register D Read: (DDRD) Write: See page 211. Reset: Port E Data Register Read: (PTE) Write: See page 213. Reset: ESCI Prescaler Register Read: (SCPSC) Write: See page 246. Reset: ESCI Arbiter Control Read: Register (SCIACTL) Write: See page 250. Reset:
Bit 7 PTA7
6 PTA6
5 PTA5
4 PTA4
3 PTA3
2 PTA2
1 PTA1
Bit 0 PTA0
Unaffected by reset PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
$0001
Unaffected by reset 1 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0
$0002
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Unaffected by reset PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
$0003
Unaffected by reset DDRA7 0 DDRB7 0 0 0 DDRD7 0 0 DDRA6 0 DDRB6 0 DDRC6 0 DDRD6 0 0 DDRA5 0 DDRB5 0 DDRC5 0 DDRD5 0 PTE5 DDRA4 0 DDRB4 0 DDRC4 0 DDRD4 0 PTE4 DDRA3 0 DDRB3 0 DDRC3 0 DDRD3 0 PTE3 DDRA2 0 DDRB2 0 DDRC2 0 DDRD2 0 PTE2 DDRA1 0 DDRB1 0 DDRC1 0 DDRD1 0 PTE1 DDRA0 0 DDRB0 0 DDRC0 0 DDRD0 0 PTE0
$0004
$0005
$0006
$0007
$0008
Unaffected by reset PS2 0 AM1 0 PS1 0 ALOST 0 = Unimplemented PS0 0 AM0 0 PSSB4 0 ACLK 0 R = Reserved PSSB3 0 AFIN 0 PSSB2 0 ARUN 0 U = Unaffected PSSB1 0 AOVFL 0 PSSB0 0 ARD8 0
$0009
$000A
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 8)
Data Sheet 32 Memory Map
MC68HC908GZ8 MOTOROLA
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Memory Map Input/Output (I/O) Section
Addr. $000B
Register Name ESCI Arbiter Data Read: Register (SCIADAT) Write: See page 251. Reset: Data Direction Register E Read: (DDRE) Write: See page 214. Reset:
Bit 7 ARD7 0 0 0
6 ARD6 0 0 0 PTAPUE6 0 PTCPUE6 0 PTDPUE6 0 R 0 ERRIE 0 R6 T6
5 ARD5 0 DDRE5 0 PTAPUE5 0 PTCPUE5 0 PTDPUE5 0 SPMSTR 1 OVRF 0 R5 T5
4 ARD4 0 DDRE4 0 PTAPUE4 0 PTCPUE4 0 PTDPUE4 0 CPOL 0 MODF 0 R4 T4
3 ARD3 0 DDRE3 0 PTAPUE3 0 PTCPUE3 0 PTDPUE3 0 CPHA 1 SPTE 1 R3 T3
2 ARD2 0 DDRE2 0 PTAPUE2 0 PTCPUE2 0 PTDPUE2 0 SPWOM 0 MODFEN 0 R2 T2
1 ARD1 0 DDRE1 0 PTAPUE1 0 PTCPUE1 0 PTDPUE1 0 SPE 0 SPR1 0 R1 T1
Bit 0 ARD0 0 DDRE0 0 PTAPUE0 0 PTCPUE0 0 PTDPUE0 0 SPTIE 0 SPR0 0 R0 T0
$000C
$000D
Port A Input Pullup Enable Read: PTAPUE7 Register (PTAPUE) Write: See page 204. Reset: 0 Port C Input Pullup Enable Read: Register (PTCPUE) Write: See page 209. Reset: 0 0
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$000E
$000F
Port D Input Pullup Enable Read: PTDPUE7 Register (PTDPUE) Write: See page 213. Reset: 0 SPI Control Register Read: (SPCR) Write: See page 293. Reset: SPI Status and Control Read: Register (SPSCR) Write: See page 295. Reset: SPI Data Register Read: (SPDR) Write: See page 297. Reset: ESCI Control Register 1 Read: (SCC1) Write: See page 235. Reset: ESCI Control Register 2 Read: (SCC2) Write: See page 237. Reset: ESCI Control Register 3 Read: (SCC3) Write: See page 239. Reset: ESCI Status Register 1 Read: (SCS1) Write: See page 241. Reset: SPRIE 0 SPRF 0 R7 T7
$0010
$0011
$0012
Unaffected by reset LOOPS 0 SCTIE 0 R8 U SCTE 1 ENSCI 0 TCIE 0 T8 0 TC 1 = Unimplemented TXINV 0 SCRIE 0 R 0 SCRF 0 M 0 ILIE 0 R 0 IDLE 0 R = Reserved WAKE 0 TE 0 ORIE 0 OR 0 ILTY 0 RE 0 NEIE 0 NF 0 U = Unaffected PEN 0 RWU 0 FEIE 0 FE 0 PTY 0 SBK 0 PEIE 0 PE 0
$0013
$0014
$0015
$0016
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 8)
MC68HC908GZ8 MOTOROLA Memory Map Data Sheet 33
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Memory Map
Addr. $0017
Register Name ESCI Status Register 2 Read: (SCS2) Write: See page 243. Reset: ESCI Data Register Read: (SCDR) Write: See page 244. Reset: ESCI Baud Rate Register Read: (SCBR) Write: See page 244. Reset: Keyboard Status Read: and Control Register Write: (INTKBSCR) See page 143. Reset: Keyboard Interrupt Enable Read: Register (INTKBIER) Write: See page 144. Reset: Timebase Module Control Read: Register (TBCR) Write: See page 302. Reset: IRQ Status and Control Read: Register (INTSCR) Write: See page 138. Reset: Configuration Register 2 Read: (CONFIG2)(1) Write: See page 104. Reset: Configuration Register 1 Read: (CONFIG1)(1) Write: See page 104. Reset:
Bit 7
6
5
4
3
2
1 BKF
Bit 0 RPF 0 R0 T0
0 R7 T7
0 R6 T6
0 R5 T5
0 R4 T4
0 R3 T3
0 R2 T2
0 R1 T1
$0018
Unaffected by reset LINT 0 0 LINR 0 0 SCP1 0 0 SCP0 0 0 R 0 KEYF SCR2 0 0 ACKK 0 KBIE7 0 TBIF 0 0 0 0 0 KBIE6 0 TBR2 0 0 0 0 0 KBIE5 0 TBR1 0 0 0 0 0 KBIE4 0 TBR0 0 0 0 0 0 KBIE3 0 0 TACK 0 IRQF1 0 0 KBIE2 0 TBIE 0 0 ACK1 0 SCR1 0 IMASKK 0 KBIE1 0 TBON 0 IMASK1 0 SCR0 0 MODEK 0 KBIE0 0 R 0 MODE1 0
$0019
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$001A
$001B
$001C
$001D
$001E
MSCAN-E OSCENINTMCLKSEL SCIBDSRC N STOP 0 LVI5OR3 (Note 1) 0 0 SSREC 0 0 STOP 0 1 COPD 0
0 COPRS 0
0 LVISTOP 0
0 LVIRSTD 0
0 LVIPWRD 0
$001F
1. One-time writable register after each reset, except LVI5OR3 bit. LVI5OR3 bit is only reset via POR (power-on reset).
Timer 1 Status and Control Read: Register (T1SC) Write: See page 315. Reset: Timer 1 Counter Read: Register High (T1CNTH) Write: See page 317. Reset: TOF 0 0 Bit 15 0 TOIE 0 14 0 = Unimplemented TSTOP 1 13 0 0 TRST 0 12 0 R = Reserved 0 11 0 0 PS2 0 10 0 U = Unaffected PS1 0 9 0 PS0 0 Bit 8 0
$0020
$0021
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 8)
Data Sheet 34 Memory Map
MC68HC908GZ8 MOTOROLA
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Memory Map Input/Output (I/O) Section
Addr. $0022
Register Name Timer 1 Counter Read: Register Low (T1CNTL) Write: See page 317. Reset: Timer 1 Counter Modulo Read: Register High (T1MODH) Write: See page 317. Reset: Timer 1 Counter Modulo Read: Register Low (T1MODL) Write: See page 318. Reset:
Bit 7 Bit 7 0 Bit 15 1 Bit 7 1 CH0F 0 0 Bit 15
6 6 0 14 1 6 1 CH0IE 0 14
5 5 0 13 1 5 1 MS0B 0 13
4 4 0 12 1 4 1 MS0A 0 12
3 3 0 11 1 3 1 ELS0B 0 11
2 2 0 10 1 2 1 ELS0A 0 10
1 1 0 9 1 1 1 TOV0 0 9
Bit 0 Bit 0 0 Bit 8 1 Bit 0 1 CH0MAX 0 Bit 8
$0023
$0024
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Timer 1 Channel 0 Status and Read: $0025 Control Register (T1SC0) Write: See page 318. Reset: $0026 Timer 1 Channel 0 Read: Register High (T1CH0H) Write: See page 321. Reset: Timer 1 Channel 0 Read: Register Low (T1CH0L) Write: See page 321. Reset:
Indeterminate after reset Bit 7 6 5 4 3 2 1 Bit 0
$0027
Indeterminate after reset CH1F 0 0 Bit 15 CH1IE 0 14 0 0 13 MS1A 0 12 ELS1B 0 11 ELS1A 0 10 TOV1 0 9 CH1MAX 0 Bit 8
Timer 1 Channel 1 Status and Read: $0028 Control Register (T1SC1) Write: See page 318. Reset: $0029 Timer 1 Channel 1 Read: Register High (T1CH1H) Write: See page 322. Reset: Timer 1 Channel 1 Read: Register Low (T1CH1L) Write: See page 322. Reset: Timer 2 Status and Control Read: Register (T2SC) Write: See page 315. Reset: Timer 2 Counter Read: Register High (T2CNTH) Write: See page 317. Reset: Timer 2 Counter Read: Register Low (T2CNTL) Write: See page 317. Reset:
Indeterminate after reset Bit 7 6 5 4 3 2 1 Bit 0
$002A
Indeterminate after reset TOF 0 0 Bit 15 0 Bit 7 0 TOIE 0 14 0 6 0 = Unimplemented TSTOP 1 13 0 5 0 0 TRST 0 12 0 4 0 R = Reserved 0 11 0 3 0 0 PS2 0 10 0 2 0 U = Unaffected PS1 0 9 0 1 0 PS0 0 Bit 8 0 Bit 0 0
$002B
$002C
$002D
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 8)
MC68HC908GZ8 MOTOROLA Memory Map Data Sheet 35
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Memory Map
Addr. $002E
Register Name Timer 2 Counter Modulo Read: Register High (T2MODH) Write: See page 317. Reset: Timer 2 Counter Modulo Read: Register Low (T2MODL) Write: See page 318. Reset:
Bit 7 Bit 15 1 Bit 7 1 CH0F 0 0 Bit 15
6 14 1 6 1 CH0IE 0 14
5 13 1 5 1 MS0B 0 13
4 12 1 4 1 MS0A 0 12
3 11 1 3 1 ELS0B 0 11
2 10 1 2 1 ELS0A 0 10
1 9 1 1 1 TOV0 0 9
Bit 0 Bit 8 1 Bit 0 1 CH0MAX 0 Bit 8
$002F
Timer 2 Channel 0 Status and Read: $0030 Control Register (T2SC0) Write: See page 318. Reset:
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$0031
Timer 2 Channel 0 Read: Register High (T2CH0H) Write: See page 321. Reset: Timer 2 Channel 0 Read: Register Low (T2CH0L) Write: See page 321. Reset: Timer 2 Channel 1 Status and Read: Control Register (T2SC1) Write: See page 318. Reset: Timer 2 Channel 1 Read: Register High (T2CH1H) Write: See page 322. Reset: Timer 2 Channel 1 Read: Register Low (T2CH1L) Write: See page 322. Reset: PLL Control Register Read: (PCTL) Write: See page 94. Reset: PLL Bandwidth Control Read: Register (PBWC) Write: See page 96. Reset: PLL Multiplier Select High Read: Register (PMSH) Write: See page 97. Reset: PLL Multiplier Select Low Read: Register (PMSL) Write: See page 98. Reset:
Indeterminate after reset Bit 7 6 5 4 3 2 1 Bit 0
$0032
Indeterminate after reset CH1F 0 0 Bit 15 CH1IE 0 14 0 0 13 MS1A 0 12 ELS1B 0 11 ELS1A 0 10 TOV1 0 9 CH1MAX 0 Bit 8
$0033
$0034
Indeterminate after reset Bit 7 6 5 4 3 2 1 Bit 0
$0035
Indeterminate after reset PLLIE 0 AUTO 0 0 0 MUL7 0 PLLF 0 LOCK 0 0 0 MUL6 0 = Unimplemented PLLON 1 ACQ 0 0 0 MUL5 0 BCS 0 0 0 0 0 MUL4 0 R = Reserved R 0 0 0 MUL11 0 MUL3 U R 0 0 0 MUL10 0 MUL2 U U = Unaffected VPR1 0 0 0 MUL9 0 MUL1 U VPR0 0 R 0 MUL8 0 MUL0 U
$0036
$0037
$0038
$0039
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 8)
Data Sheet 36 Memory Map MC68HC908GZ8 MOTOROLA
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Memory Map Input/Output (I/O) Section
Addr. $003A
Register Name PLL VCO Select Range Read: Register (PMRS) Write: See page 98. Reset: Read: Reserved Write: Reset:
Bit 7 VRS7 0 0 0 COCO 0 0
6 VRS6 1 0 0 AIEN 0 0
5 VRS5 0 0 0 ADCO 0 0
4 VRS4 0 0 0 ADCH4 1 0
3 VRS3 0 R 0 ADCH3 1 0
2 VRS2 0 R 0 ADCH2 1 0
1 VRS1 0 R 0 ADCH1 1 AD9
Bit 0 VRS0 0 R 1 ADCH0 1 AD8
$003B
$003C
ADC Status and Control Read: Register (ADSCR) Write: See page 71. Reset: ADC Data High Register Read: (ADRH) Write: See page 73. Reset: ADC Data Low Register Read: (ADRL) Write: See page 73. Reset: ADC Clock Register Read: (ADCLK) Write: See page 75. Reset: MSCAN08 Control Registers See page 183.
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$003D
Unaffected by reset AD7 AD6 AD5 AD4 A3 AD2 AD1 AD0
$003E
Unaffected by reset ADIV2 0 ADIV1 0 ADIV0 0 ADICLK 0 MODE1 0 MODE0 1 R 0 0 0
$003F $0500 $0508 $0509 $050D $050E $050F $0510 $0517 $0518 $053F
MSCAN08 control registers (9 bytes) Refer to 16.13 Programmer's Model of Control Registers
Reserved
Reserved (5 bytes)
MSCAN08 Error Counters
MSCAN08 error counters (2 bytes)
MSCAN08 Identifier Filter See page 183.
MSCAN08 control registers (9 bytes) Refer to 16.13 Programmer's Model of Control Registers
Reserved
Reserved (40 bytes)
= Unimplemented
R = Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 8)
MC68HC908GZ8 MOTOROLA Memory Map
Data Sheet 37
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Memory Map
Addr. $0540 $054F $0550 $055F $0560 $056F $0570 $057F
Register Name MSCAN08 Receive Buffer See page 179.
Bit 7
6
5
4
3
2
1
Bit 0
MSC08 receive buffer Refer to 16.12 Programmer's Model of Message Storage
MSCAN08 Transmit Buffer 0 See page 179.
MSC08 transmitter buffer 0 Refer to 16.12 Programmer's Model of Message Storage
MSCAN08 Transmit Buffer 1 See page 179.
MSC08 transmitter buffer 1 Refer to 16.12 Programmer's Model of Message Storage
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MSCAN08 Transmit Buffer 2 See page 179.
MSC08 transmitter buffer 2 Refer to 16.12 Programmer's Model of Message Storage
$FE00
Break Status Register Read: (BSR) Write: See page 81. Reset: SIM Reset Status Register Read: (SRSR) Write: See page 272. POR: Read: Reserved Write: Reset: Break Flag Control Register Read: (BFCR) Write: See page 82. Reset: Interrupt Status Register 1 Read: (INT1) Write: See page 62. Reset: Interrupt Status Register 2 Read: (INT2) Write: See page 62. Reset: Interrupt Status Register 3 Read: (INT3) Write: See page 63. Reset:
R 0 POR 1 R 0 BCFE 0 IF6 R 0 IF14 R 0 0 R 0
R 0 PIN 0 R 0 R 0 IF5 R 0 IF13 R 0 0 R 0
R 0 COP 0 R 0 R 0 IF4 R 0 IF12 R 0 IF20 R 0
R 0 ILOP 0 R 0 R 0 IF3 R 0 IF11 R 0 IF19 R 0 R = Reserved
R 0 ILAD 0 R 0 R 0 IF2 R 0 IF10 R 0 IF18 R 0
R 0 MODRST 0 R 0 R 0 IF1 R 0 IF9 R 0 IF17 R 0
SBSW (Note 2) 0 LVI 0 R 0 R 0 0 R 0 IF8 R 0 IF16 R 0
R 0 0 0 R 0 R 0 0 R 0 IF7 R 0 IF15 R 0
2. Writing a logic 0 clears SBSW. $FE01
$FE02
$FE03
$FE04
$FE05
$FE06
= Unimplemented
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 8)
Data Sheet 38 Memory Map MC68HC908GZ8 MOTOROLA
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Memory Map Input/Output (I/O) Section
Addr. $FE07
Register Name Read: Reserved Write: Reset: FLASH Control Register Read: (FLCR) Write: See page 126. Reset:
Bit 7 R 0 0 0 Bit 15 0 Bit 7 0 BRKE 0 LVIOUT 0 BPR7
6 R 0 0 0 14 0 6 0 BRKA 0 0 0 BPR6
5 R 0 0 0 13 0 5 0 0 0 0 0 BPR5
4 R 0 0 0 12 0 4 0 0 0 0 0 BPR4
3 R 0 HVEN 0 11 0 3 0 0 0 0 0 BPR3
2 R 0 MASS 0 10 0 2 0 0 0 0 0 BPR2
1 R 0 ERASE 0 9 0 1 0 0 0 0 0 BPR1
Bit 0 R 0 PGM 0 Bit 8 0 Bit 0 0 0 0 0 0 BPR0
$FE08
Break Address Register High Read: $FE09 (BRKH) Write: See page 81. Reset:
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Break Address Register Low Read: $FE0A (BRKL) Write: See page 81. Reset: $FE0B Break Status and Control Read: Register (BRKSCR) Write: See page 80. Reset: LVI Status Register Read: (LVISR) Write: See page 147. Reset: FLASH Block Protect Read: Register (FLBPR)(3) Write: See page 132. Reset: COP Control Register Read: (COPCTL) Write: See page 109. Reset:
$FE0C
$FF7E
Unaffected by reset Low byte of reset vector Writing clears COP counter (any value) Unaffected by reset = Unimplemented R = Reserved U = Unaffected
3. Non-volatile FLASH register $FFFF
Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 8)
MC68HC908GZ8 MOTOROLA Memory Map
Data Sheet 39
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Memory Map
Table 2-1. Vector Addresses
Vector Priority Lowest Vector IF20 IF19 IF18 IF17 IF16 IF15 IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 IF6 IF5 IF4 IF3 IF2 IF1 -- -- Address $FFD4 $FFD5 $FFD6 $FFD7 $FFD8 $FFD9 $FFDA $FFDB $FFDC $FFDD $FFDE $FFDF $FFE0 $FFE1 $FFE2 $FFE3 $FFE4 $FFE5 $FFE6 $FFE7 $FFE8 $FFE9 $FFEA $FFEB $FFEC $FFED $FFEE $FFEF $FFF0 $FFF1 $FFF2 $FFF3 $FFF4 $FFF5 $FFF6 $FFF7 $FFF8 $FFF9 $FFFA $FFFB $FFFC $FFFD $FFFE $FFFF Vector MSCAN08 Transmit Vector (High) MSCAN08 Transmit Vector (Low) MSCAN08 Receive Vector (High) MSCAN08 Receive Vector (Low) MSCAN08 Error Vector (High) MSCAN08 Error Vector (Low) MSCAN08 Wakeup Vector (High) MSCAN08 Wakeup Vector (Low) Timebase Vector (High) Timebase Vector (Low) ADC Conversion Complete Vector (High) ADC Conversion Complete Vector (Low) Keyboard Vector (High) Keyboard Vector (Low) ESCI Transmit Vector (High) ESCI Transmit Vector (Low) ESCI Receive Vector (High) ESCI Receive Vector (Low) ESCI Error Vector (High) ESCI Error Vector (Low) SPI Transmit Vector (High) SPI Transmit Vector (Low) SPI Receive Vector (High) SPI Receive Vector (Low) TIM2 Overflow Vector (High) TIM2 Overflow Vector (Low) TIM2 Channel 1 Vector (High) TIM2 Channel 1 Vector (Low) TIM2 Channel 0 Vector (High) TIM2 Channel 0 Vector (Low) TIM1 Overflow Vector (High) TIM1 Overflow Vector (Low) TIM1 Channel 1 Vector (High) TIM1 Channel 1 Vector (Low) TIM1 Channel 0 Vector (High) TIM1 Channel 0 Vector (Low) PLL Vector (High) PLL Vector (Low) IRQ Vector (High) IRQ Vector (Low) SWI Vector (High) SWI Vector (Low) Reset Vector (High) Reset Vector (Low)
.
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Highest
Data Sheet 40 Memory Map
MC68HC908GZ8 MOTOROLA
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Data Sheet -- MC68HC908GZ8
Section 3. Low-Power Modes
3.1 Introduction
The microcontroller (MCU) may enter two low-power modes: wait mode and stop mode. They are common to all HC08 MCUs and are entered through instruction execution. This section describes how each module acts in the low-power modes. 3.1.1 Wait Mode The WAIT instruction puts the MCU in a low-power standby mode in which the central processor unit (CPU) clock is disabled but the bus clock continues to run. Power consumption can be further reduced by disabling the low-voltage inhibit (LVI) module through bits in the CONFIG1 register. See Section 8. Configuration Register (CONFIG). 3.1.2 Stop Mode Stop mode is entered when a STOP instruction is executed. The CPU clock is disabled and the bus clock is disabled if the OSCENINSTOP bit in the CONFIG2 register is at a logic 0. See Section 8. Configuration Register (CONFIG).
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3.2 Analog-to-Digital Converter (ADC)
3.2.1 Wait Mode The analog-to-digital converter (ADC) continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power down the ADC by setting ADCH4-ADCH0 bits in the ADC status and control register before executing the WAIT instruction. 3.2.2 Stop Mode The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode after an external interrupt. Allow one conversion cycle to stabilize the analog circuitry.
MC68HC908GZ8 MOTOROLA Low-Power Modes
Data Sheet 41
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Low-Power Modes
3.3 Break Module (BRK)
3.3.1 Wait Mode If enabled, the break (BRK) module is active in wait mode. In the break routine, the user can subtract one from the return address on the stack if the SBSW bit in the break status register is set. 3.3.2 Stop Mode The break module is inactive in stop mode. The STOP instruction does not affect break module register states.
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3.4 Clock Generator Module (CGM)
3.4.1 Wait Mode The clock generator module (CGM) remains active in wait mode. Before entering wait mode, software can disengage and turn off the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL). Less power-sensitive applications can disengage the PLL without turning it off. Applications that require the PLL to wake the MCU from wait mode also can deselect the PLL output without turning off the PLL. 3.4.2 Stop Mode If the OSCSTOPEN bit in the CONFIG register is cleared (default), then the STOP instruction disables the CGM (oscillator and phase-locked loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and CGMINT). If the STOP instruction is executed with the VCO clock, CGMVCLK, divided by two driving CGMOUT, the PLL automatically clears the BCS bit in the PLL control register (PCTL), thereby selecting the crystal clock, CGMXCLK, divided by two as the source of CGMOUT. When the MCU recovers from STOP, the crystal clock divided by two drives CGMOUT and BCS remains clear. If the OSCSTOPEN bit in the CONFIG register is set, then the phase locked loop is shut off, but the oscillator will continue to operate in stop mode.
3.5 Computer Operating Properly Module (COP)
3.5.1 Wait Mode The COP remains active during wait mode. If COP is enabled, a reset will occur at COP timeout.
Data Sheet 42 Low-Power Modes
MC68HC908GZ8 MOTOROLA
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Low-Power Modes Central Processor Unit (CPU)
3.5.2 Stop Mode Stop mode turns off the COPCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. The STOP bit in the CONFIG1 register enables the STOP instruction. To prevent inadvertently turning off the COP with a STOP instruction, disable the STOP instruction by clearing the STOP bit.
3.6 Central Processor Unit (CPU)
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3.6.1 Wait Mode The WAIT instruction: * Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock
* 3.6.2 Stop Mode
The STOP instruction: * Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock
*
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
3.7 External Interrupt Module (IRQ)
3.7.1 Wait Mode The external interrupt (IRQ) module remains active in wait mode. Clearing the IMASK1 bit in the IRQ status and control register enables IRQ CPU interrupt requests to bring the MCU out of wait mode. 3.7.2 Stop Mode The IRQ module remains active in stop mode. Clearing the IMASK1 bit in the IRQ status and control register enables IRQ CPU interrupt requests to bring the MCU out of stop mode.
MC68HC908GZ8 MOTOROLA Low-Power Modes
Data Sheet 43
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Low-Power Modes
3.8 Keyboard Interrupt Module (KBI)
3.8.1 Wait Mode The keyboard interrupt (KBI) module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode. 3.8.2 Stop Mode The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode.
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3.9 Low-Voltage Inhibit Module (LVI)
3.9.1 Wait Mode If enabled, the low-voltage inhibit (LVI) module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode. 3.9.2 Stop Mode If enabled, the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode.
3.10 Motorola Scalable Controller Area Network Module (MSCAN)
3.10.1 Wait Mode The Motorola scalable controller area network (MSCAN) module remains active after execution of the WAIT instruction. In wait mode, the MSCAN08 registers are not accessible by the CPU. If the MSCAN08 functions are not required during wait mode, reduce the power consumption by disabling the MSCAN08 module before enabling the WAIT instruction. 3.10.2 Stop Mode The MSCAN08 module is inactive in stop mode. The STOP instruction does not affect MSCAN08 register states. Because the internal clock is inactive during stop mode, entering stop mode during an MSCAN08 transmission or reception results in invalid data.
Data Sheet 44 Low-Power Modes
MC68HC908GZ8 MOTOROLA
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Low-Power Modes Enhanced Serial Communications Interface Module (ESCI)
3.11 Enhanced Serial Communications Interface Module (ESCI)
3.11.1 Wait Mode The enhanced serial communications interface (ESCI), or SCI module for short, module remains active in wait mode. Any enabled CPU interrupt request from the SCI module can bring the MCU out of wait mode. If SCI module functions are not required during wait mode, reduce power consumption by disabling the module before executing the WAIT instruction. 3.11.2 Stop Mode
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The SCI module is inactive in stop mode. The STOP instruction does not affect SCI register states. SCI module operation resumes after the MCU exits stop mode. Because the internal clock is inactive during stop mode, entering stop mode during an SCI transmission or reception results in invalid data.
3.12 Serial Peripheral Interface Module (SPI)
3.12.1 Wait Mode The serial peripheral interface (SPI) module remains active in wait mode. Any enabled CPU interrupt request from the SPI module can bring the MCU out of wait mode. If SPI module functions are not required during wait mode, reduce power consumption by disabling the SPI module before executing the WAIT instruction. 3.12.2 Stop Mode The SPI module is inactive in stop mode. The STOP instruction does not affect SPI register states. SPI operation resumes after an external interrupt. If stop mode is exited by reset, any transfer in progress is aborted, and the SPI is reset.
3.13 Timebase Module (TBM)
3.13.1 Wait Mode The timebase module (TBM) remains active after execution of the WAIT instruction. In wait mode, the timebase register is not accessible by the CPU. If the timebase functions are not required during wait mode, reduce the power consumption by stopping the timebase before enabling the WAIT instruction.
MC68HC908GZ8 MOTOROLA Low-Power Modes
Data Sheet 45
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Low-Power Modes
3.13.2 Stop Mode The timebase module may remain active after execution of the STOP instruction if the oscillator has been enabled to operate during stop mode through the OSCENINSTOP bit in the CONFIG2 register. The timebase module can be used in this mode to generate a periodic wakeup from stop mode. If the oscillator has not been enabled to operate in stop mode, the timebase module will not be active during stop mode. In stop mode, the timebase register is not accessible by the CPU. If the timebase functions are not required during stop mode, reduce the power consumption by stopping the timebase before enabling the STOP instruction.
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3.14 Timer Interface Module (TIM1 and TIM2)
3.14.1 Wait Mode The timer interface modules (TIM) remain active in wait mode. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode. If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction. 3.14.2 Stop Mode The TIM is inactive in stop mode. The STOP instruction does not affect register states or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode after an external interrupt.
3.15 Exiting Wait Mode
These events restart the CPU clock and load the program counter with the reset vector or with an interrupt vector: * * External reset -- A logic 0 on the RST pin resets the MCU and loads the program counter with the contents of locations $FFFE and $FFFF. External interrupt -- A high-to-low transition on an external interrupt pin (IRQ pin) loads the program counter with the contents of locations: $FFFA and $FFFB; IRQ pin. Break interrupt -- In emulation mode, a break interrupt loads the program counter with the contents of $FFFC and $FFFD. Computer operating properly (COP) module reset -- A timeout of the COP counter resets the MCU and loads the program counter with the contents of $FFFE and $FFFF.
* *
Data Sheet 46 Low-Power Modes
MC68HC908GZ8 MOTOROLA
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Low-Power Modes Exiting Wait Mode
*
Low-voltage inhibit (LVI) module reset -- A power supply voltage below the VTRIPF voltage resets the MCU and loads the program counter with the contents of locations $FFFE and $FFFF. Clock generator module (CGM) interrupt -- A CPU interrupt request from the ICG loads the program counter with the contents of $FFF8 and $FFF9. Keyboard interrupt (KBI) module -- A CPU interrupt request from the KBI module loads the program counter with the contents of $FFE0 and $FFE1. Timer 1 interface (TIM1) module interrupt -- A CPU interrupt request from the TIM1 loads the program counter with the contents of: - $FFF2 and $FFF3; TIM1 overflow - $FFF4 and $FFF5; TIM1 channel 1 - $FFF6 and $FFF7; TIM1 channel 0 Timer 2 interface (TIM2) module interrupt -- A CPU interrupt request from the TIM2 loads the program counter with the contents of: - $FFEC and $FFED; TIM2 overflow - $FFEE and $FFEF; TIM2 channel 1 - $FFF0 and $FFF1; TIM2 channel 0 Serial peripheral interface (SPI) module interrupt -- A CPU interrupt request from the SPI loads the program counter with the contents of: - $FFE8 and $FFE9; SPI transmitter - $FFEA and $FFEB; SPI receiver Serial communications interface (SCI) module interrupt -- A CPU interrupt request from the SCI loads the program counter with the contents of: - $FFE2 and $FFE3; SCI transmitter - $FFE4 and $FFE5; SCI receiver - $FFE6 and $FFE7; SCI receiver error Analog-to-digital converter (ADC) module interrupt -- A CPU interrupt request from the ADC loads the program counter with the contents of: $FFDE and $FFDF; ADC conversion complete. Timebase module (TBM) interrupt -- A CPU interrupt request from the TBM loads the program counter with the contents of: $FFDC and $FFDD; TBM interrupt. Motorola scalable controller area network (MSCAN) module interrupt -- A CPU interrupt request from the MSCAN08 loads the program counter with the contents of: - $FFD4 and $FFD5; MSCAN08 transmitter - $FFD6 and $FFD7; MSCAN08 receiver - $FFD8 and $FFD9; MSCAN08 error - $FFDA and $FFDB; MSCAN08 wakeup
* * *
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*
*
*
*
*
*
MC68HC908GZ8 MOTOROLA Low-Power Modes
Data Sheet 47
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Low-Power Modes
3.16 Exiting Stop Mode
These events restart the system clocks and load the program counter with the reset vector or with an interrupt vector: * * External reset -- A logic 0 on the RST pin resets the MCU and loads the program counter with the contents of locations $FFFE and $FFFF. External interrupt -- A high-to-low transition on an external interrupt pin loads the program counter with the contents of locations: - $FFFA and $FFFB; IRQ pin - $FFE0 and $FFE1; keyboard interrupt pins Low-voltage inhibit (LVI) reset -- A power supply voltage below the LVITRIPF voltage resets the MCU and loads the program counter with the contents of locations $FFFE and $FFFF. Timebase module (TBM) interrupt -- A TBM interrupt loads the program counter with the contents of locations $FFDC and $FFDD when the timebase counter has rolled over. This allows the TBM to generate a periodic wakeup from stop mode. MSCAN08 interrupt -- MSCAN08 bus activity can wake the MCU from CPU stop. However, until the oscillator starts up and synchronization is achieved the MSCAN08 will not respond to incoming data.
*
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*
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Upon exit from stop mode, the system clocks begin running after an oscillator stabilization delay. A 12-bit stop recovery counter inhibits the system clocks for 4096 CGMXCLK cycles after the reset or external interrupt. The short stop recovery bit, SSREC, in the CONFIG1 register controls the oscillator stabilization delay during stop recovery. Setting SSREC reduces stop recovery time from 4096 CGMXCLK cycles to 32 CGMXCLK cycles. NOTE: Use the full stop recovery time (SSREC = 0) in applications that use an external crystal.
Data Sheet 48 Low-Power Modes
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Data Sheet -- MC68HC908GZ8
Section 4. Resets and Interrupts
4.1 Introduction
Resets and interrupts are responses to exceptional events during program execution. A reset re-initializes the microcontroller (MCU) to its startup condition. An interrupt vectors the program counter to a service routine.
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4.2 Resets
A reset immediately returns the MCU to a known startup condition and begins program execution from a user-defined memory location. 4.2.1 Effects A reset: * * * * 4.2.2 External Reset A logic 0 applied to the RST pin for a time, tRL, generates an external reset. An external reset sets the PIN bit in the system integration module (SIM) reset status register. 4.2.3 Internal Reset Sources: * * * * * Power-on reset (POR) Computer operating properly (COP) Low-power reset circuits Illegal opcode Illegal address Immediately stops the operation of the instruction being executed Initializes certain control and status bits Loads the program counter with a user-defined reset vector address from locations $FFFE and $FFFF Selects CGMXCLK divided by four as the bus clock
MC68HC908GZ8 MOTOROLA Resets and Interrupts
Data Sheet 49
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Resets and Interrupts
All internal reset sources pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external devices. The MCU is held in reset for an additional 32 CGMXCLK cycles after releasing the RST pin. 4.2.3.1 Power-On Reset (POR) A power-on reset (POR) is an internal reset caused by a positive transition on the VDD pin. VDD at the POR must below VPOR to reset the MCU. This distinguishes between a reset and a POR. The POR is not a brown-out detector, low-voltage detector, or glitch detector. A power-on reset:
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* * * * *
Holds the clocks to the central processor unit (CPU) and modules inactive for an oscillator stabilization delay of 4096 CGMXCLK cycles Drives the RST pin low during the oscillator stabilization delay Releases the RST pin 32 CGMXCLK cycles after the oscillator stabilization delay Releases the CPU to begin the reset vector sequence 64 CGMXCLK cycles after the oscillator stabilization delay Sets the POR and LVI bits in the SIM reset status register and clears all other bits in the register
OSC1 PORRST(1) 4096 CYCLES CGMXCLK CGMOUT RST PIN 1. PORRST is an internally generated power-on reset pulse. 32 CYCLES
Figure 4-1. Power-On Reset Recovery 4.2.3.2 Computer Operating Properly (COP) Reset A computer operating properly (COP) reset is an internal reset caused by an overflow of the COP counter. A COP reset sets the COP bit in the SIM reset status register. To clear the COP counter and prevent a COP reset, write any value to the COP control register at location $FFFF.
Data Sheet 50 Resets and Interrupts
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Resets and Interrupts Resets
4.2.3.3 Low-Voltage Inhibit (LVI) Reset A low-voltage inhibit (LVI) reset is an internal reset caused by a drop in the power supply voltage to the LVITRIPF voltage. An LVI reset: * Holds the clocks to the CPU and modules inactive for an oscillator stabilization delay of 4096 CGMXCLK cycles after the power supply voltage rises to the LVITRIPR voltage Drives the RST pin low for as long as VDD is below the LVITRIPR voltage and during the oscillator stabilization delay Releases the RST pin 32 CGMXCLK cycles after the oscillator stabilization delay Releases the CPU to begin the reset vector sequence 64 CGMXCLK cycles after the oscillator stabilization delay Sets the LVI bit in the SIM reset status register
*
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* * *
4.2.3.4 Illegal Opcode Reset An illegal opcode reset is an internal reset caused by an opcode that is not in the instruction set. An illegal opcode reset sets the ILOP bit in the SIM reset status register. If the stop enable bit, STOP, in the mask option register is a logic 0, the STOP instruction causes an illegal opcode reset. 4.2.3.5 Illegal Address Reset An illegal address reset is an internal reset caused by opcode fetch from an unmapped address. An illegal address reset sets the ILAD bit in the SIM reset status register. A data fetch from an unmapped address does not generate a reset. 4.2.4 System Integration Module (SIM) Reset Status Register This read-only register contains flags to show reset sources. All flag bits are automatically cleared following a read of the register. Reset service can read the SIM reset status register to clear the register after power-on reset and to determine the source of any subsequent reset. The register is initialized on power-up as shown with the POR bit set and all other bits cleared. During a POR or any other internal reset, the RST pin is pulled low. After the pin is released, it will be sampled 32 CGMXCLK cycles later. If the pin is not above a VIH at that time, then the PIN bit in the SRSR may be set in addition to whatever other bits are set.
MC68HC908GZ8 MOTOROLA Resets and Interrupts
Data Sheet 51
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Resets and Interrupts
NOTE: Only a read of the SIM reset status register clears all reset flags. After multiple resets from different sources without reading the register, multiple flags remain set.
Address: Read: Write: POR: 1 0 0 0 0 0 0 0 = Unimplemented $FE01 Bit 7 POR 6 PIN 5 COP 4 ILOP 3 ILAD 2 MODRST 1 LVI Bit 0 0
Figure 4-2. SIM Reset Status Register (SRSR)
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POR -- Power-On Reset Flag 1 = Power-on reset since last read of SRSR 0 = Read of SRSR since last power-on reset PIN -- External Reset Flag 1 = External reset via RST pin since last read of SRSR 0 = POR or read of SRSR since last external reset COP -- Computer Operating Properly Reset Bit 1 = Last reset caused by timeout of COP counter 0 = POR or read of SRSR since any reset ILOP -- Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR since any reset ILAD -- Illegal Address Reset Bit 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR since any reset MODRST -- Monitor Mode Entry Module Reset Bit 1 = Last reset caused by forced monitor mode entry. 0 = POR or read of SRSR since any reset LVI -- Low-Voltage Inhibit Reset Bit 1 = Last reset caused by low-power supply voltage 0 = POR or read of SRSR since any reset
Data Sheet 52 Resets and Interrupts
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Resets and Interrupts Interrupts
4.3 Interrupts
An interrupt temporarily changes the sequence of program execution to respond to a particular event. An interrupt does not stop the operation of the instruction being executed, but begins when the current instruction completes its operation. 4.3.1 Effects An interrupt: * Saves the CPU registers on the stack. At the end of the interrupt, the RTI instruction recovers the CPU registers from the stack so that normal processing can resume. Sets the interrupt mask (I bit) to prevent additional interrupts. Once an interrupt is latched, no other interrupt can take precedence, regardless of its priority. Loads the program counter with a user-defined vector address
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*
*
* * *
5 4 STACKING ORDER 3 2 1
CONDITION CODE REGISTER ACCUMULATOR INDEX REGISTER (LOW BYTE)(1) PROGRAM COUNTER (HIGH BYTE) PROGRAM COUNTER (LOW BYTE)
1 2 3 4 5 UNSTACKING ORDER
* * *
$00FF DEFAULT ADDRESS ON RESET 1. High byte of index register is not stacked.
Figure 4-3. Interrupt Stacking Order After every instruction, the CPU checks all pending interrupts if the I bit is not set. If more than one interrupt is pending when an instruction is done, the highest priority interrupt is serviced first. In the example shown in Figure 4-4, if an interrupt is pending upon exit from the interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed.
MC68HC908GZ8 MOTOROLA Resets and Interrupts Data Sheet 53
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Resets and Interrupts
CLI LDA #$FF BACKGROUND ROUTINE
INT1
PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI
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INT2
PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI
Figure 4-4. Interrupt Recognition Example The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation. NOTE: To maintain compatibility with the M6805 Family, the H register is not pushed on the stack during interrupt entry. If the interrupt service routine modifies the H register or uses the indexed addressing mode, save the H register and then restore it prior to exiting the routine. See Figure 4-5 for a flowchart depicting interrupt processing. 4.3.2 Sources The sources in Table 4-1 can generate CPU interrupt requests.
Data Sheet 54 Resets and Interrupts
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Resets and Interrupts Interrupts
FROM RESET
BREAK INTERRUPT ? NO YES
YES
BIT SET? IIBIT SET? NO IRQ INTERRUPT ? NO CGM INTERRUPT ? NO YES
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YES
OTHER INTERRUPTS ? NO
YES
STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR
FETCH NEXT INSTRUCTION
SWI INSTRUCTION ? NO RTI INSTRUCTION ? NO
YES
YES
UNSTACK CPU REGISTERS
EXECUTE INSTRUCTION
Figure 4-5. Interrupt Processing
MC68HC908GZ8 MOTOROLA Resets and Interrupts
Data Sheet 55
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Resets and Interrupts
Table 4-1. Interrupt Sources
Source Reset SWI instruction IRQ pin CGM change in lock TIM1 channel 0 TIM1 channel 1 TIM1 overflow Flag None None IRQF PLLF CH0F CH1F TOF CH0F CH1F TOF SPRF OVRF MODF SPTE OR NF FE PE SCRF IDLE SCTE TC KEYF COCO TBIF WUPIF RWRNIF TWRNIF RERIF TERRIF BOFFIF OVRIF RXF TXE2 TXE1 TXE0 Mask(1) None None IMASK1 PLLIE CH0IE CH1IE TOIE CH0IE CH1IE TOIE SPRIE ERRIE ERRIE SPTIE ORIE NEIE FEIE PEIE SCRIE ILIE SCTIE TCIE IMASKK AIEN TBIE WUPIE RWRNIE TWRNIE RERRIE TERRIE BOFFIE OVRIE RXFIE TXEIE2 TXEIE1 TXEIE0 IF12 IF13 IF14 IF15 IF16 IF17 12 13 14 15 16 17 $FFE4-$FFE5 $FFE2-$FFE3 $FFE0-$FFE1 $FFDE-$FFDF $FFDC-$FFDD $FFDA-$FFDB IF11 11 $FFE6-$FFE7 IF10 10 $FFE8-$FFE9 IF9 9 $FFEA-$FFEB INT Register Flag None None IF1 IF2 IF3 IF4 IF5 IF6 IF7 IF8 Priority(2) 0 0 1 2 3 4 5 6 7 8 Vector Address $FFFE-$FFFF $FFFC-$FFFD $FFFA-$FFFB $FFF8-$FFF9 $FFF6-$FFF7 $FFF4-$FFF5 $FFF2-$FFF3 $FFF0-$FFF1 $FFEE-$FFEF $FFEC-$FFED
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TIM2 channel 0 TIM2 channel 1 TIM2 overflow SPI receiver full SPI overflow SPI mode fault SPI transmitter empty SCI receiver overrun SCI noise flag SCI framing error SCI parity error SCI receiver full SCI input idle SCI transmitter empty SCI transmission complete Keyboard pin ADC conversion complete Timebase MSCAN08 receiver wakeup
MSCAN08 error
IF18
18
$FFD8-$FFD9
MSCAN08 receiver MSCAN08 transmitter
IF19 IF20
19 20
$FFD6-$FFD7 $FFD4-$FFD5
1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction. 2. 0 = highest priority
Data Sheet 56 Resets and Interrupts
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Resets and Interrupts Interrupts
4.3.2.1 Software Interrupt (SWI) Instruction The software interrupt (SWI) instruction causes a non-maskable interrupt. NOTE: A software interrupt pushes PC onto the stack. An SWI does not push PC - 1, as a hardware interrupt does.
4.3.2.2 Break Interrupt The break module causes the CPU to execute an SWI instruction at a software-programmable break point.
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4.3.2.3 IRQ Pin A logic 0 on the IRQ pin latches an external interrupt request. 4.3.2.4 Clock Generator (CGM) The CGM can generate a CPU interrupt request every time the phase-locked loop circuit (PLL) enters or leaves the locked state. When the LOCK bit changes state, the PLL flag (PLLF) is set. The PLL interrupt enable bit (PLLIE) enables PLLF CPU interrupt requests. LOCK is in the PLL bandwidth control register. PLLF is in the PLL control register. 4.3.2.5 Timer Interface Module 1 (TIM1) TIM1 CPU interrupt sources: * TIM1 overflow flag (TOF) -- The TOF bit is set when the TIM1 counter value rolls over to $0000 after matching the value in the TIM1 counter modulo registers. The TIM1 overflow interrupt enable bit, TOIE, enables TIM1 overflow CPU interrupt requests. TOF and TOIE are in the TIM1 status and control register. TIM1 channel flags (CH1F-CH0F) -- The CHxF bit is set when an input capture or output compare occurs on channel x. The channel x interrupt enable bit, CHxIE, enables channel x TIM1 CPU interrupt requests. CHxF and CHxIE are in the TIM1 channel x status and control register.
*
4.3.2.6 Timer Interface Module 2 (TIM2) TIM2 CPU interrupt sources: * TIM2 overflow flag (TOF) -- The TOF bit is set when the TIM2 counter value rolls over to $0000 after matching the value in the TIM2 counter modulo registers. The TIM2 overflow interrupt enable bit, TOIE, enables TIM2 overflow CPU interrupt requests. TOF and TOIE are in the TIM2 status and control register.
MC68HC908GZ8 MOTOROLA Resets and Interrupts
Data Sheet 57
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Resets and Interrupts
* TIM2 channel flags (CH1F-CH0F) -- The CHxF bit is set when an input capture or output compare occurs on channel x. The channel x interrupt enable bit, CHxIE, enables channel x TIM2 CPU interrupt requests. CHxF and CHxIE are in the TIM2 channel x status and control register.
4.3.2.7 Serial Peripheral Interface (SPI) SPI CPU interrupt sources: * SPI receiver full bit (SPRF) -- The SPRF bit is set every time a byte transfers from the shift register to the receive data register. The SPI receiver interrupt enable bit, SPRIE, enables SPRF CPU interrupt requests. SPRF is in the SPI status and control register and SPRIE is in the SPI control register. SPI transmitter empty (SPTE) -- The SPTE bit is set every time a byte transfers from the transmit data register to the shift register. The SPI transmit interrupt enable bit, SPTIE, enables SPTE CPU interrupt requests. SPTE is in the SPI status and control register and SPTIE is in the SPI control register. Mode fault bit (MODF) -- The MODF bit is set in a slave SPI if the SS pin goes high during a transmission with the mode fault enable bit (MODFEN) set. In a master SPI, the MODF bit is set if the SS pin goes low at any time with the MODFEN bit set. The error interrupt enable bit, ERRIE, enables MODF CPU interrupt requests. MODF, MODFEN, and ERRIE are in the SPI status and control register. Overflow bit (OVRF) -- The OVRF bit is set if software does not read the byte in the receive data register before the next full byte enters the shift register. The error interrupt enable bit, ERRIE, enables OVRF CPU interrupt requests. OVRF and ERRIE are in the SPI status and control register.
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*
*
*
4.3.2.8 Serial Communications Interface (SCI) SCI CPU interrupt sources: * SCI transmitter empty bit (SCTE) -- SCTE is set when the SCI data register transfers a character to the transmit shift register. The SCI transmit interrupt enable bit, SCTIE, enables transmitter CPU interrupt requests. SCTE is in SCI status register 1. SCTIE is in SCI control register 2. Transmission complete bit (TC) -- TC is set when the transmit shift register and the SCI data register are empty and no break or idle character has been generated. The transmission complete interrupt enable bit, TCIE, enables transmitter CPU interrupt requests. TC is in SCI status register 1. TCIE is in SCI control register 2. SCI receiver full bit (SCRF) -- SCRF is set when the receive shift register transfers a character to the SCI data register. The SCI receive interrupt enable bit, SCRIE, enables receiver CPU interrupts. SCRF is in SCI status register 1. SCRIE is in SCI control register 2.
MC68HC908GZ8 Resets and Interrupts MOTOROLA
*
*
Data Sheet 58
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Resets and Interrupts Interrupts
*
Idle input bit (IDLE) -- IDLE is set when 10 or 11 consecutive logic 1s shift in from the RxD pin. The idle line interrupt enable bit, ILIE, enables IDLE CPU interrupt requests. IDLE is in SCI status register 1. ILIE is in SCI control register 2. Receiver overrun bit (OR) -- OR is set when the receive shift register shifts in a new character before the previous character was read from the SCI data register. The overrun interrupt enable bit, ORIE, enables OR to generate SCI error CPU interrupt requests. OR is in SCI status register 1. ORIE is in SCI control register 3. Noise flag (NF) -- NF is set when the SCI detects noise on incoming data or break characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, enables NF to generate SCI error CPU interrupt requests. NF is in SCI status register 1. NEIE is in SCI control register 3. Framing error bit (FE) -- FE is set when a logic 0 occurs where the receiver expects a stop bit. The framing error interrupt enable bit, FEIE, enables FE to generate SCI error CPU interrupt requests. FE is in SCI status register 1. FEIE is in SCI control register 3. Parity error bit (PE) -- PE is set when the SCI detects a parity error in incoming data. The parity error interrupt enable bit, PEIE, enables PE to generate SCI error CPU interrupt requests. PE is in SCI status register 1. PEIE is in SCI control register 3.
*
*
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4.3.2.9 KBD0-KBD7 Pins A logic 0 on a keyboard interrupt pin latches an external interrupt request. 4.3.2.10 Analog-to-Digital Converter (ADC) When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC conversion. The COCO bit is not used as a conversion complete flag when interrupts are enabled. 4.3.2.11 Timebase Module (TBM) The timebase module can interrupt the CPU on a regular basis with a rate defined by TBR2-TBR0. When the timebase counter chain rolls over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase interrupt, the counter chain overflow will generate a CPU interrupt request. Interrupts must be acknowledged by writing a logic 1 to the TACK bit.
MC68HC908GZ8 MOTOROLA Resets and Interrupts
Data Sheet 59
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Resets and Interrupts
4.3.2.12 Motorola Scalable Controller Area Network Module (MSCAN) MSCAN08 interrupt sources: * MSCAN08 transmitter empty bits (TXE0-TXE2) -- The TXEx bit is set when the corresponding MSCAN08 data buffer is empty. The MSCAN08 transmit interrupt enable bits, TXEIE0-TXEIE2, enables transmitter CPU interrupt requests. TXEx is in MSCAN08 transmitter flag register. TXEIEx is in MSCAN08 transmitter control register. MSCAN08 receiver full bit (RXF) -- The RXF bit is set when the a MSCAN08 message has been successfully received and loaded into the foreground receive buffer. The MSCAN08 receive interrupt enable bit, RXFIE, enables receiver CPU interrupt requests. RXF is in MSCAN08 receiver flag register. RXFIE is in MSCAN08 receiver interrupt enable register. MSCAN08 wakeup bit (WUPIF) -- WUPIF is set when activity on the CAN bus occurred during the MSCAN08 internal sleep mode. The wakeup interrupt enable bit, WUPIE, enables MSCAN08 wakeup CPU interrupt requests. WUPIF is in MSCAN08 receiver flag register. WUPIE is in MSCAN08 receiver interrupt enable register. Overrun bit (OVRIF) -- OVRIF is set when both the foreground and the background receive message buffers are filled with correctly received messages and a further message is being received from the bus. The overrun interrupt enable bit, OVRIE, enables OVRIF to generate MSCAN08 error CPU interrupt requests. OVRIF is in MSCAN08 receiver flag register. OVRIE is in MSCAN08 receiver interrupt enable register. Receiver Warning bit (RWRNIF) -- RWRNIF is set when the receive error counter has reached the CPU warning limit of 96. The receiver warning interrupt enable bit, RWRNIE, enables RWRNIF to generate MSCAN08 error CPU interrupt requests. RWRNIF is in MSCAN08 receiver flag register. RWRNIE is in MSCAN08 receiver interrupt enable register. Transmitter Warning bit (TWRNIF) -- TWRNIF is set when the transmit error counter has reached the CPU warning limit of 96. The transmitter warning interrupt enable bit, TWRNIF, enables TWRNIF to generate MSCAN08 error CPU interrupt requests. TWRNIF is in MSCAN08 receiver flag register. TWRNIE is in MSCAN08 receiver interrupt enable register. Receiver Error Passive bit (RERRIF) -- RERRIF is set when the receive error counter has exceeded the error passive limit of 127 and the MSCAN08 has gone to error passive state. The receiver error passive interrupt enable bit, RERRIE, enables RERRIF to generate MSCAN08 error CPU interrupt requests. RERRIF is in MSCAN08 receiver flag register. RERRIE is in MSCAN08 receiver interrupt enable register. Transmitter Error Passive bit (TERRIF) -- TERRIF is set when the transmit error counter has exceeded the error passive limit of 127 and the MSCAN08 has gone to error passive state. The transmit error passive interrupt enable bit, TERRIE, enables TERRIF to generate MSCAN08 error CPU interrupt
*
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*
*
*
*
Data Sheet 60 Resets and Interrupts
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Resets and Interrupts Interrupts
requests. TERRIF is in MSCAN08 receiver flag register. TERRIE is in MSCAN08 receiver interrupt enable register. * Bus Off bit (BOFFIF) -- BOFFIF is set when the transmit error counter has exceeded 255 and MSCAN08 has gone to bus off state. The bus off interrupt enable bit, BOFFIE, enables BOFFIF to generate MSCAN08 error CPU interrupt requests. BOFFIF is in MSCAN08 receiver flag register. BOFFIE is in MSCAN08 receiver interrupt enable register.
4.3.3 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources. Table 4-2 summarizes the interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be useful for debugging. Table 4-2. Interrupt Source Flags
Interrupt Source Reset SWI instruction IRQ pin CGM change of lock TIM1 channel 0 TIM1 channel 1 TIM1 overflow TIM2 channel 0 TIM2 channel 1 TIM2 overflow SPI receive SPI transmit SCI error SCI receive SCI transmit Keyboard ADC conversion complete Timebase MSCAN08 wakeup MSCAN08 error MSCAN08 receive MSCAN08 transmit Interrupt Status Register Flag -- -- IF1 IF2 IF3 IF4 IF5 IF6 IF7 IF8 IF9 IF10 IF11 IF12 IF13 IF14 IF15 IF16 IF17 IF18 IF19 IF20
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MC68HC908GZ8 MOTOROLA
Data Sheet Resets and Interrupts 61
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Resets and Interrupts
4.3.3.1 Interrupt Status Register 1
Address: Read: Write: Reset: $FE04 Bit 7 IF6 R 0 R 6 IF5 R 0 = Reserved 5 IF4 R 0 4 IF3 R 0 3 IF2 R 0 2 IF1 R 0 1 0 R 0 Bit 0 0 R 0
Figure 4-6. Interrupt Status Register 1 (INT1)
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IF6-IF1 -- Interrupt Flags 6-1 These flags indicate the presence of interrupt requests from the sources shown in Table 4-2. 1 = Interrupt request present 0 = No interrupt request present Bit 1 and Bit 0 -- Always read 0 4.3.3.2 Interrupt Status Register 2
Address: Read: Write: Reset: $FE05 Bit 7 IF14 R 0 R 6 IF13 R 0 = Reserved 5 IF12 R 0 4 IF11 R 0 3 IF10 R 0 2 IF9 R 0 1 IF8 R 0 Bit 0 IF7 R 0
Figure 4-7. Interrupt Status Register 2 (INT2) IF14-IF7 -- Interrupt Flags 14-7 These flags indicate the presence of interrupt requests from the sources shown in Table 4-2. 1 = Interrupt request present 0 = No interrupt request present
Data Sheet 62 Resets and Interrupts
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4.3.3.3 Interrupt Status Register 3
Address: Read: Write: Reset: $FE06 Bit 7 0 R 0 R 6 0 R 0 = Reserved 5 IF20 R 0 4 IF19 R 0 3 IF18 R 0 2 IF17 R 0 1 IF16 R 0 Bit 0 IF15 R 0
Figure 4-8. Interrupt Status Register 3 (INT3)
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IF20-IF15 -- Interrupt Flags 20-15 This flag indicates the presence of an interrupt request from the source shown in Table 4-2. 1 = Interrupt request present 0 = No interrupt request present Bits 7-6 -- Always read 0
MC68HC908GZ8 MOTOROLA Resets and Interrupts
Data Sheet 63
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Resets and Interrupts
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Data Sheet 64 Resets and Interrupts
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Data Sheet -- MC68HC908GZ8
Section 5. Analog-to-Digital Converter (ADC)
5.1 Introduction
This section describes the 10-bit analog-to-digital converter (ADC).
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5.2 Features
Features of the ADC module include: * * * * * * * * Eight channels with multiplexed input Linear successive approximation with monotonicity 10-bit resolution Single or continuous conversion Conversion complete flag or conversion complete interrupt Selectable ADC clock Left or right justified result Left justified sign data mode
5.3 Functional Description
The ADC provides eight pins for sampling external sources at pins PTB7/KBD7-PTB0/KBD0. An analog multiplexer allows the single ADC converter to select one of eight ADC channels as ADC voltage in (VADIN). VADIN is converted by the successive approximation register-based analog-to-digital converter. When the conversion is completed, ADC places the result in the ADC data register and sets a flag or generates an interrupt. See Figure 5-1. 5.3.1 ADC Port I/O Pins PTB7/AD7-PTB0/AD0 are general-purpose I/O (input/output) pins that share with the ADC channels. The channel select bits define which ADC channel/port pin will be used as the input signal. The ADC overrides the port I/O logic by forcing that pin as input to the ADC. The remaining ADC channels/port pins are controlled by the port I/O logic and can be used as general-purpose I/O. Writes to the port register or data direction register (DDR) will not have any affect on the port pin that is selected by the ADC. Read of a port pin in use by the ADC will return a logic 0.
MC68HC908GZ8 MOTOROLA Analog-to-Digital Converter (ADC)
Data Sheet 65
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Analog-to-Digital Converter (ADC)
INTERNAL DATA BUS READ DDRBx WRITE DDRBx RESET WRITE PTBx DDRBx PTBx PTBx ADC CHANNEL x DISABLE
READ PTBx
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DISABLE ADC DATA REGISTER
INTERRUPT LOGIC
CONVERSION COMPLETE
ADC
ADC VOLTAGE IN (VADIN)
CHANNEL SELECT
ADCH4-ADCH0
AIEN
COCO CGMXCLK BUS CLOCK
ADC CLOCK
CLOCK GENERATOR
ADIV2-ADIV0
ADICLK
Figure 5-1. ADC Block Diagram 5.3.2 Voltage Conversion When the input voltage to the ADC equals VREFH, the ADC converts the signal to $3FF (full scale). If the input voltage equals VREFL, the ADC converts it to $000. Input voltages between VREFH and VREFL are a straight-line linear conversion. NOTE: The ADC input voltage must always be greater than VSSAD and less than VDDAD. Connect the VDDAD pin to the same voltage potential as the VDD pin, and connect the VSSAD pin to the same voltage potential as the VSS pin. The VDDAD pin should be routed carefully for maximum noise immunity.
Data Sheet 66 Analog-to-Digital Converter (ADC)
MC68HC908GZ8 MOTOROLA
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Analog-to-Digital Converter (ADC) Functional Description
5.3.3 Conversion Time Conversion starts after a write to the ADC status and control register (ADSCR). One conversion will take between 16 and 17 ADC clock cycles. The ADIVx and ADICLK bits should be set to provide a 1-MHz ADC clock frequency. Conversion time = 16 to 17 ADC cycles ADC frequency
Number of bus cycles = conversion time x bus frequency 5.3.4 Conversion
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In continuous conversion mode, the ADC data register will be filled with new data after each conversion. Data from the previous conversion will be overwritten whether that data has been read or not. Conversions will continue until the ADCO bit is cleared. The COCO bit is set after each conversion and will stay set until the next read of the ADC data register. In single conversion mode, conversion begins with a write to the ADSCR. Only one conversion occurs between writes to the ADSCR. When a conversion is in process and the ADCSCR is written, the current conversion data should be discarded to prevent an incorrect reading. 5.3.5 Accuracy and Precision The conversion process is monotonic and has no missing codes. 5.3.6 Result Justification The conversion result may be formatted in four different ways: 1. Left justified 2. Right justified 3. Left Justified sign data mode 4. 8-bit truncation mode All four of these modes are controlled using MODE0 and MODE1 bits located in the ADC clock register (ADCLK). Left justification will place the eight most significant bits (MSB) in the corresponding ADC data register high, ADRH. This may be useful if the result is to be treated as an 8-bit result where the two least significant bits (LSB), located in the ADC data register low, ADRL, can be ignored. However, ADRL must be read after ADRH or else the interlocking will prevent all new conversions from being stored.
MC68HC908GZ8 MOTOROLA Analog-to-Digital Converter (ADC)
Data Sheet 67
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Analog-to-Digital Converter (ADC)
Right justification will place only the two MSBs in the corresponding ADC data register high, ADRH, and the eight LSBs in ADC data register low, ADRL. This mode of operation typically is used when a 10-bit unsigned result is desired. Left justified sign data mode is similar to left justified mode with one exception. The MSB of the 10-bit result, AD9 located in ADRH, is complemented. This mode of operation is useful when a result, represented as a signed magnitude from mid-scale, is needed. Finally, 8-bit truncation mode will place the eight MSBs in the ADC data register low, ADRL. The two LSBs are dropped. This mode of operation is used when compatibility with 8-bit ADC designs are required. No interlocking between ADRH and ADRL is present.
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NOTE:
Quantization error is affected when only the most significant eight bits are used as a result. See Figure 5-2.
8-BIT 10-BIT RESULT RESULT 003 00B 00A 009 002 008 007 006 005 001 004 003 002 001 000 000 1/2
IDEAL 8-BIT CHARACTERISTIC WITH QUANTIZATION = 1/2 10-BIT TRUNCATED TO 8-BIT RESULT
IDEAL 10-BIT CHARACTERISTIC WITH QUANTIZATION = 1/2
WHEN TRUNCATION IS USED, ERROR FROM IDEAL 8-BIT = 3/8 LSB DUE TO NON-IDEAL QUANTIZATION.
2 1/2 1 1/2 1/2 3 1/2
4 1/2 5 1/2
6 1/2 7 1/2 1 1/2
8 1/2 9 1/2 2 1/2
INPUT VOLTAGE REPRESENTED AS 10-BIT INPUT VOLTAGE REPRESENTED AS 8-BIT
Figure 5-2. Bit Truncation Mode Error
Data Sheet 68 Analog-to-Digital Converter (ADC)
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Analog-to-Digital Converter (ADC) Monotonicity
5.4 Monotonicity
The conversion process is monotonic and has no missing codes.
5.5 Interrupts
When the AIEN bit is set, the ADC module is capable of generating CPU interrupts after each ADC conversion. A CPU interrupt is generated if the COCO bit is at logic 0. The COCO bit is not used as a conversion complete flag when interrupts are enabled.
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5.6 Low-Power Modes
The WAIT and STOP instruction can put the MCU in low power- consumption standby modes. 5.6.1 Wait Mode The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power down the ADC by setting ADCH4-ADCH0 bits in the ADC status and control register before executing the WAIT instruction. 5.6.2 Stop Mode The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode after an external interrupt. Allow one conversion cycle to stabilize the analog circuitry.
5.7 I/O Signals
The ADC module has eight pins shared with port B, PTB7/AD7-PTB0/AD0. 5.7.1 ADC Analog Power Pin (VDDAD) The ADC analog portion uses VDDAD as its power pin. Connect the VDDAD pin to the same voltage potential as VDD. External filtering may be necessary to ensure clean VDDAD for good results. NOTE: For maximum noise immunity, route VDDAD carefully and place bypass capacitors as close as possible to the package. VDDAD and VREFH are double-bonded on the MC68HC908GZ8.
MC68HC908GZ8 MOTOROLA Analog-to-Digital Converter (ADC)
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Analog-to-Digital Converter (ADC)
5.7.2 ADC Analog Ground Pin (VSSAD) The ADC analog portion uses VSSAD as its ground pin. Connect the VSSAD pin to the same voltage potential as VSS. NOTE: Route VSSAD cleanly to avoid any offset errors. VSSAD and VREFL are double-bonded on the MC68HC908GZ8. 5.7.3 ADC Voltage Reference High Pin (VREFH) The ADC analog portion uses VREFH as its upper voltage reference pin. By default, connect the VREFH pin to the same voltage potential as VDD. External filtering is often necessary to ensure a clean VREFH for good results. Any noise present on this pin will be reflected and possibly magnified in A/D conversion values. NOTE: For maximum noise immunity, route VREFH carefully and place bypass capacitors as close as possible to the package. Routing VREFH close and parallel to VREFL may improve common mode noise rejection. VDDAD and VREFH are double-bonded on the MC68HC908GZ8. 5.7.4 ADC Voltage Reference Low Pin (VREFL) The ADC analog portion uses VREFL as its lower voltage reference pin. By default, connect the VREFH pin to the same voltage potential as VSS. External filtering is often necessary to ensure a clean VREFL for good results. Any noise present on this pin will be reflected and possibly magnified in A/D conversion values. NOTE: For maximum noise immunity, route VREFL carefully and, if not connected to VSS, place bypass capacitors as close as possible to the package. Routing VREFH close and parallel to VREFL may improve common mode noise rejection. VSSAD and VREFL are double-bonded on the MC68HC908GZ8. 5.7.5 ADC Voltage In (VADIN) VADIN is the input voltage signal from one of the eight ADC channels to the ADC module.
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Data Sheet 70 Analog-to-Digital Converter (ADC)
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Analog-to-Digital Converter (ADC) I/O Registers
5.8 I/O Registers
These I/O registers control and monitor ADC operation: * * * ADC status and control register (ADSCR) ADC data register (ADRH and ADRL) ADC clock register (ADCLK)
5.8.1 ADC Status and Control Register Function of the ADC status and control register (ADSCR) is described here.
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Address: Read: Write: Reset:
$003C Bit 7 COCO 0 6 AIEN 0 5 ADCO 0 4 ADCH4 1 3 ADCH3 1 2 ADCH2 1 1 ADCH1 1 Bit 0 ADCH0 1
Figure 5-3. ADC Status and Control Register (ADSCR) COCO -- Conversions Complete Bit In non-interrupt mode (AIEN = 0), COCO is a read-only bit that is set at the end of each conversion. COCO will stay set until cleared by a read of the ADC data register. Reset clears this bit. In interrupt mode (AIEN = 1), COCO is a read-only bit that is not set at the end of a conversion. It always reads as a logic 0. 1 = Conversion completed (AIEN = 0) 0 = Conversion not completed (AIEN = 0) or CPU interrupt enabled (AIEN = 1) AIEN -- ADC Interrupt Enable Bit When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit. 1 = ADC interrupt enabled 0 = ADC interrupt disabled ADCO -- ADC Continuous Conversion Bit When set, the ADC will convert samples continuously and update the ADR register at the end of each conversion. Only one conversion is completed between writes to the ADSCR when this bit is cleared. Reset clears the ADCO bit. 1 = Continuous ADC conversion 0 = One ADC conversion
MC68HC908GZ8 MOTOROLA Analog-to-Digital Converter (ADC)
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Analog-to-Digital Converter (ADC)
ADCH4-ADCH0 -- ADC Channel Select Bits ADCH4-ADCH0 form a 5-bit field which is used to select one of 16 ADC channels. Only eight channels, AD7-AD0, are available on this MCU. The channels are detailed in Table 5-1. Care should be taken when using a port pin as both an analog and digital input simultaneously to prevent switching noise from corrupting the analog signal. See Table 5-1. The ADC subsystem is turned off when the channel select bits are all set to 1. This feature allows for reduced power consumption for the MCU when the ADC is not being used. NOTE: Recovery from the disabled state requires one conversion cycle to stabilize. The voltage levels supplied from internal reference nodes, as specified in Table 5-1, are used to verify the operation of the ADC converter both in production test and for user applications. Table 5-1. Mux Channel Select(1)
ADCH4 0 0 0 0 0 0 0 0 0 1 1 1 1 ADCH3 0 0 0 0 0 0 0 0 1 1 1 1 1 ADCH2 0 0 0 0 1 1 1 1 0 1 1 1 1 ADCH1 0 0 1 1 0 0 1 1 0 0 0 1 1 ADCH0 0 1 0 1 0 1 0 1 0 0 1 0 1 VREFH VREFL ADC power off Unused Input Select PTB0/AD0 PTB1/AD1 PTB2/AD2 PTB3/AD3 PTB4/AD4 PTB5/AD5 PTB6/AD6 PTB7/AD7
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1. If any unused channels are selected, the resulting ADC conversion will be unknown or reserved.
Data Sheet 72 Analog-to-Digital Converter (ADC)
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Analog-to-Digital Converter (ADC) I/O Registers
5.8.2 ADC Data Register High and Data Register Low 5.8.2.1 Left Justified Mode In left justified mode, the ADRH register holds the eight MSBs of the 10-bit result. The only difference from left justified mode is that the AD9 is complemented. The ADRL register holds the two LSBs of the 10-bit result. All other bits read as 0. ADRH and ADRL are updated each time an ADC single channel conversion completes. Reading ADRH latches the contents of ADRL until ADRL is read. All subsequent results will be lost until the ADRH and ADRL reads are completed.
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Address:
$003D Bit 7 6 AD8 5 AD7 4 AD6 3 AD5 2 AD4 1 AD3
ADRH Bit 0 AD2
Read: Write: Reset: Address: Read: Write: Reset:
AD9
Unaffected by reset $003E AD1 AD0 0 0 0 0 0 ADRL 0
Unaffected by reset = Unimplemented
Figure 5-4. ADC Data Register High (ADRH) and Low (ADRL) 5.8.2.2 Right Justified Mode In right justified mode, the ADRH register holds the two MSBs of the 10-bit result. All other bits read as 0. The ADRL register holds the eight LSBs of the 10-bit result. ADRH and ADRL are updated each time an ADC single channel conversion completes. Reading ADRH latches the contents of ADRL until ADRL is read. All subsequent results will be lost until the ADRH and ADRL reads are completed.
Address: $003D Bit 7 Read: Write: Reset: Address: Read: Write: Reset: = Unimplemented Unaffected by reset $003E AD7 AD6 AD5 AD4 AD3 AD2 AD1 Unaffected by reset ADRL AD0 0 6 0 5 0 4 0 3 0 2 0 1 AD9 ADRH Bit 0 AD8
Figure 5-5. ADC Data Register High (ADRH) and Low (ADRL)
MC68HC908GZ8 MOTOROLA Analog-to-Digital Converter (ADC)
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Analog-to-Digital Converter (ADC)
5.8.2.3 Left Justified Signed Data Mode In left justified signed data mode, the ADRH register holds the eight MSBs of the 10-bit result. The only difference from left justified mode is that the AD9 is complemented. The ADRL register holds the two LSBs of the 10-bit result. All other bits read as 0. ADRH and ADRL are updated each time an ADC single channel conversion completes. Reading ADRH latches the contents of ADRL until ADRL is read. All subsequent results will be lost until the ADRH and ADRL reads are completed.
Address: $003D Bit 7 6 AD8 5 AD7 4 AD6 3 AD5 2 AD4 1 AD3 Bit 0 AD2
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Read: Write: Reset: Address: Read: Write: Reset:
AD9
Unaffected by reset $003E AD1 AD0 0 0 0 0 0 0
Unaffected by reset = Unimplemented
Figure 5-6. ADC Data Register High (ADRH) and Low (ADRL) 5.8.2.4 Eight Bit Truncation Mode In 8-bit truncation mode, the ADRL register holds the eight MSBs of the 10-bit result. The ADRH register is unused and reads as 0. The ADRL register is updated each time an ADC single channel conversion completes. In 8-bit mode, the ADRL register contains no interlocking with ADRH.
Address: $003D Bit 7 Read: Write: Reset: Address: Read: Write: Reset: = Unimplemented Unaffected by reset $003E AD9 AD8 AD7 AD6 AD5 AD4 AD3 Unaffected by reset ADRL AD2 0 6 0 5 0 4 0 3 0 2 0 1 0 ADRH Bit 0 0
Figure 5-7. ADC Data Register High (ADRH) and Low (ADRL)
Data Sheet 74 Analog-to-Digital Converter (ADC)
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Analog-to-Digital Converter (ADC) I/O Registers
5.8.3 ADC Clock Register The ADC clock register (ADCLK) selects the clock frequency for the ADC.
Address: $003F Bit 7 Read: Write: Reset: ADIV2 0 6 ADIV1 0 5 ADIV0 0 4 ADICLK 0 R 3 MODE1 0 = Reserved 2 MODE0 1 1 R 0 Bit 0 0 0
= Unimplemented
Figure 5-8. ADC Clock Register (ADCLK)
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ADIV2-ADIV0 -- ADC Clock Prescaler Bits ADIV2-ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock. Table 5-2 shows the available clock configurations. The ADC clock should be set to approximately 1 MHz. Table 5-2. ADC Clock Divide Ratio
ADIV2 0 0 0 0 1 ADIV1 0 0 1 1 X(1) ADIV0 0 1 0 1 X(1) ADC Clock Rate ADC input clock / 1 ADC input clock / 2 ADC input clock / 4 ADC input clock / 8 ADC input clock / 16
1. X = Don't care
ADICLK -- ADC Input Clock Select Bit ADICLK selects either the bus clock or the oscillator output clock (CGMXCLK) as the input clock source to generate the internal ADC clock. Reset selects CGMXCLK as the ADC clock source. 1 = Internal bus clock 0 = Oscillator output clock (CGMXCLK) The ADC requires a clock rate of approximately 1 MHz for correct operation. If the selected clock source is not fast enough, the ADC will generate incorrect conversions. See 24.10 5.0-Volt ADC Characteristics. fADIC = fCGMXCLK or bus frequency ADIV[2:0] 1 MHz
MC68HC908GZ8 MOTOROLA Analog-to-Digital Converter (ADC)
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Analog-to-Digital Converter (ADC)
MODE1 and MODE0 -- Modes of Result Justification Bits MODE1 and MODE0 select among four modes of operation. The manner in which the ADC conversion results will be placed in the ADC data registers is controlled by these modes of operation. Reset returns right-justified mode. 00 = 8-bit truncation mode 01 = Right justified mode 10 = Left justified mode 11 = Left justified signed data mode
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Data Sheet 76 Analog-to-Digital Converter (ADC)
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Data Sheet -- MC68HC908GZ8
Section 6. Break Module (BRK)
6.1 Introduction
This section describes the break module. The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program.
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6.2 Features
Features of the break module include: * * * * Accessible input/output (I/O) registers during the break Interrupt Central processor unit (CPU) generated break interrupts Software-generated break interrupts Computer operating properly (COP) disabling during break interrupts
6.3 Functional Description
When the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal (BKPT) to the system integration module (SIM). The SIM then causes the CPU to load the instruction register with a software interrupt instruction (SWI). The program counter vectors to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode). The following events can cause a break interrupt to occur: * * A CPU generated address (the address in the program counter) matches the contents of the break address registers. Software writes a logic 1 to the BRKA bit in the break status and control register.
When a CPU generated address matches the contents of the break address registers, the break interrupt is generated. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the microcontroller unit (MCU) to normal operation. Figure 6-1 shows the structure of the break module. Figure 6-2 provides a summary of the I/O registers.
MC68HC908GZ8 MOTOROLA Break Module (BRK)
Data Sheet 77
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Break Module (BRK)
ADDRESS BUS[15:8]
BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR ADDRESS BUS[15:0] CONTROL 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW BKPT (TO SIM)
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ADDRESS BUS[7:0]
Figure 6-1. Break Module Block Diagram
Addr.
Register Name Break Status Register Read: (BSR) Write: See page 81. Reset: Read:
Bit 7 R
6 R
5 R
4 R
3 R
2 R
1 SBSW Note(1) 0
Bit 0 R
$FE00
$FE02
Reserved Write: Reset: Break Flag Control Read: Register (BFCR) Write: See page 82. Reset: Break Address High Read: Register (BRKH) Write: See page 81. Reset: Break Address Low Read: Register (BRKL) Write: See page 81. Reset: Break Status and Control Read: Register (BRKSCR) Write: See page 80. Reset:
R 0 BCFE 0 Bit15 0 Bit 7 0 BRKE 0
R 0 R
R 0 R
R 0 R
R 0 R
R 0 R
R 0 R
R 0 R
$FE03
$FE09
Bit14 0 Bit 6 0 BRKA 0
Bit13 0 Bit 5 0 0
Bit12 0 Bit 4 0 0
Bit11 0 Bit 3 0 0
Bit10 0 Bit 2 0 0
Bit9 0 Bit 1 0 0
Bit8 0 Bit 0 0 0
$FE0A
$FE0B
0
0 R
0 = Reserved
0
0
0
1. Writing a logic 0 clears SBSW.
= Unimplemented
Figure 6-2. Break I/O Register Summary
Data Sheet 78 Break Module (BRK)
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Break Module (BRK) Functional Description
When the internal address bus matches the value written in the break address registers or when software writes a logic 1 to the BRKA bit in the break status and control register, the CPU starts a break interrupt by: * * Loading the instruction register with the SWI instruction Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode)
The break interrupt timing is: * When a break address is placed at the address of the instruction opcode, the instruction is not executed until after completion of the break interrupt routine. When a break address is placed at an address of an instruction operand, the instruction is executed before the break interrupt. When software writes a logic 1 to the BRKA bit, the break interrupt occurs just before the next instruction is executed.
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* *
By updating a break address and clearing the BRKA bit in a break interrupt routine, a break interrupt can be generated continuously.
CAUTION:
A break address should be placed at the address of the instruction opcode. When software does not change the break address and clears the BRKA bit in the first break interrupt routine, the next break interrupt will not be generated after exiting the interrupt routine even when the internal address bus matches the value written in the break address registers.
6.3.1 Flag Protection During Break Interrupts The system integration module (SIM) controls whether or not module status bits can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. See 20.7.3 Break Flag Control Register and the Break Interrupts subsection for each module. 6.3.2 TIM During Break Interrupts A break interrupt stops the timer counter. 6.3.3 COP During Break Interrupts The COP is disabled during a break interrupt when VTST is present on the RST pin.
MC68HC908GZ8 MOTOROLA Break Module (BRK)
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Break Module (BRK)
6.4 Break Module Registers
These registers control and monitor operation of the break module: * * * * * Break status and control register (BRKSCR) Break address register high (BRKH) Break address register low (BRKL) Break status register (BSR) Break flag control register (BFCR)
6.4.1 Break Status and Control Register
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The break status and control register (BRKSCR) contains break module enable and status bits.
Address: $FE0B Bit 7 Read: Write: Reset: BRKE 0 6 BRKA 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0
= Unimplemented
Figure 6-3. Break Status and Control Register (BRKSCR) BRKE -- Break Enable Bit This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic 0 to bit 7. Reset clears the BRKE bit. 1 = Breaks enabled on 16-bit address match 0 = Breaks disabled BRKA -- Break Active Bit This read/write status and control bit is set when a break address match occurs. Writing a logic 1 to BRKA generates a break interrupt. Clear BRKA by writing a logic 0 to it before exiting the break routine. Reset clears the BRKA bit. 1 = Break address match 0 = No break address match
Data Sheet 80 Break Module (BRK)
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Break Module (BRK) Break Module Registers
6.4.2 Break Address Registers The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers.
Address: $FE09 Bit 7 Read: Write: Reset: Bit 15 0 6 Bit 14 0 5 Bit 13 0 4 Bit 12 0 3 Bit 11 0 2 Bit 10 0 1 Bit 9 0 Bit 0 Bit 8 0
Figure 6-4. Break Address Register High (BRKH)
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Address: $FE0A Bit 7 Read: Write: Reset: Bit 7 0 6 Bit 6 0 5 Bit 5 0 4 Bit 4 0 3 Bit 3 0 2 Bit 2 0 1 Bit 1 0 Bit 0 Bit 0 0
Figure 6-5. Break Address Register Low (BRKL) 6.4.3 Break Status Register The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode. This register is only used in emulation mode.
Address: $FE00 Bit 7 Read: Write: Reset: R = Reserved R 6 R 5 R 4 R 3 R 2 R 1 SBSW Note(1) 0 1. Writing a logic 0 clears SBSW. Bit 0 R
Figure 6-6. Break Status Register (BSR) SBSW -- SIM Break Stop/Wait SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. 1 = Wait mode was exited by break interrupt 0 = Wait mode was not exited by break interrupt
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Data Sheet 81
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Break Module (BRK)
6.4.4 Break Flag Control Register The break control register (BFCR) contains a bit that enables software to clear status bits while the MCU is in a break state.
Address: $FE03 Bit 7 Read: Write: Reset: BCFE 0 R = Reserved 6 R 5 R 4 R 3 R 2 R 1 R Bit 0 R
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Figure 6-7. Break Flag Control Register (BFCR) BCFE -- Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break
6.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes. If enabled, the break module will remain enabled in wait and stop modes. However, since the internal address bus does not increment in these modes, a break interrupt will never be triggered.
Data Sheet 82 Break Module (BRK)
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Data Sheet -- MC68HC908GZ8
Section 7. Clock Generator Module (CGM)
7.1 Introduction
This section describes the clock generator module. The CGM generates the crystal clock signal, CGMXCLK, which operates at the frequency of the crystal. The CGM also generates the base clock signal, CGMOUT, which is based on either the crystal clock divided by two or the phase-locked loop (PLL) clock, CGMVCLK, divided by two. In user mode, CGMOUT is the clock from which the SIM derives the system clocks, including the bus clock, which is at a frequency of CGMOUT/2. The PLL is a fully functional frequency generator designed for use with crystals or ceramic resonators. The PLL can generate a maximum bus frequency of 8 MHz using a 1-8MHz crystal or external clock source.
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7.2 Features
Features of the CGM include: * Phase-locked loop with output frequency in integer multiples of an integer dividend of the crystal reference * High-frequency crystal operation with low-power operation and high-output frequency resolution * Programmable hardware voltage-controlled oscillator (VCO) for low-jitter operation * Automatic bandwidth control mode for low-jitter operation * Automatic frequency lock detector * CPU interrupt on entry or exit from locked condition * Configuration register bit to allow oscillator operation during stop mode
7.3 Functional Description
The CGM consists of three major submodules: * Crystal oscillator circuit -- The crystal oscillator circuit generates the constant crystal frequency clock, CGMXCLK. * Phase-locked loop (PLL) -- The PLL generates the programmable VCO frequency clock, CGMVCLK. * Base clock selector circuit -- This software-controlled circuit selects either CGMXCLK divided by two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The SIM derives the system clocks from either CGMOUT or CGMXCLK.
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Clock Generator Module (CGM)
Figure 7-1 shows the structure of the CGM.
OSCILLATOR (OSC) OSC2 CGMXCLK (TO: SIM, TIMTB15A, ADC) OSC1
SIMOSCEN (FROM SIM) OSCSTOPENB (FROM CONFIG)
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PHASE-LOCKED LOOP (PLL)
CGMRCLK BCS CLOCK SELECT CIRCUIT /2
A B S*
CGMOUT (TO SIM) SIMDIV2 (FROM SIM)
VDDA
CGMXFC
VSSA VPR1-VPR0 VRS7-VRS0
*WHEN S = 1,
CGMOUT = B
PHASE DETECTOR
LOOP FILTER PLL ANALOG
VOLTAGE CONTROLLED OSCILLATOR
CGMVCLK
LOCK DETECTOR
AUTOMATIC MODE CONTROL
INTERRUPT CONTROL
CGMINT (TO SIM)
LOCK MUL11-MUL0
AUTO
ACQ
PLLIE
PLLF
CGMVDV
FREQUENCY DIVIDER
Figure 7-1. CGM Block Diagram
Data Sheet 84 Clock Generator Module (CGM)
MC68HC908GZ8 MOTOROLA
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Clock Generator Module (CGM) Functional Description
7.3.1 Crystal Oscillator Circuit The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal from the system integration module (SIM) or the OSCSTOPENB bit in the CONFIG register enable the crystal oscillator circuit. The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. CGMXCLK is then buffered to produce CGMRCLK, the PLL reference clock. CGMXCLK can be used by other modules which require precise timing for operation. The duty cycle of CGMXCLK is not guaranteed to be 50% and depends on external factors, including the crystal and related external components. An externally generated clock also can feed the OSC1 pin of the crystal oscillator circuit. Connect the external clock to the OSC1 pin and let the OSC2 pin float. 7.3.2 Phase-Locked Loop Circuit (PLL) The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes either automatically or manually. 7.3.3 PLL Circuits The PLL consists of these circuits: * Voltage-controlled oscillator (VCO) * Modulo VCO frequency divider * Phase detector * Loop filter * Lock detector The operating range of the VCO is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and CGMXFC noise. The VCO frequency is bound to a range from roughly one-half to twice the center-of-range frequency, fVRS. Modulating the voltage on the CGMXFC pin changes the frequency within this range. By design, fVRS is equal to the nominal center-of-range frequency, fNOM, (71.4 kHz) times a linear factor, L, and a power-of-two factor, E, or (L x 2E)fNOM. CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK. CGMRCLK runs at a frequency, fRCLK. The VCO's output clock, CGMVCLK, running at a frequency, fVCLK, is fed back through a programmable modulo divider. The modulo divider reduces the VCO clock by a factor, N. The dividers output is the VCO feedback clock, CGMVDV, running at a frequency, fVDV = fVCLK/(N). (For more information, see 7.3.6 Programming the PLL.)
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MC68HC908GZ8 MOTOROLA Clock Generator Module (CGM)
Data Sheet 85
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Clock Generator Module (CGM)
The phase detector then compares the VCO feedback clock, CGMVDV, with the final reference clock, CGMRDV. A correction pulse is generated based on the phase difference between the two signals. The loop filter then slightly alters the DC voltage on the external capacitor connected to CGMXFC based on the width and direction of the correction pulse. The filter can make fast or slow corrections depending on its mode, described in 7.3.4 Acquisition and Tracking Modes. The value of the external capacitor and the reference frequency determines the speed of the corrections and the stability of the PLL. The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the reference clock, CGMRCLK. Therefore, the speed of the lock detector is directly proportional to the reference frequency, fRCLK. The circuit determines the mode of the PLL and the lock condition based on this comparison. 7.3.4 Acquisition and Tracking Modes The PLL filter is manually or automatically configurable into one of two operating modes: * Acquisition mode -- In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL start up or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency. When in acquisition mode, the ACQ bit is clear in the PLL bandwidth control register. (See 7.5.2 PLL Bandwidth Control Register.) Tracking mode -- In tracking mode, the filter makes only small corrections to the frequency of the VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL enters tracking mode when the VCO frequency is nearly correct, such as when the PLL is selected as the base clock source. (See 7.3.8 Base Clock Selector Circuit.) The PLL is automatically in tracking mode when not in acquisition mode or when the ACQ bit is set.
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*
7.3.5 Manual and Automatic PLL Bandwidth Modes The PLL can change the bandwidth or operational mode of the loop filter manually or automatically. Automatic mode is recommended for most users. In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. (See 7.5.2 PLL Bandwidth Control Register.) If PLL interrupts are enabled, the software can wait for a PLL interrupt request and then check the LOCK bit. If interrupts are disabled, software can poll the LOCK bit continuously (for example, during PLL start up) or at periodic intervals. In either case, when the LOCK bit is set, the VCO clock is safe to use as the source for the base clock. (See 7.3.8 Base Clock Selector Circuit.) If the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has suffered a severe noise hit and the software must take appropriate action,
Data Sheet 86 Clock Generator Module (CGM) MC68HC908GZ8 MOTOROLA
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Clock Generator Module (CGM) Functional Description
depending on the application. (See 7.6 Interrupts for information and precautions on using interrupts.) The following conditions apply when the PLL is in automatic bandwidth control mode: * The ACQ bit (See 7.5.2 PLL Bandwidth Control Register.) is a read-only indicator of the mode of the filter. (See 7.3.4 Acquisition and Tracking Modes.) The ACQ bit is set when the VCO frequency is within a certain tolerance and is cleared when the VCO frequency is out of a certain tolerance. (See 7.8 Acquisition/Lock Time Specifications for more information.) The LOCK bit is a read-only indicator of the locked state of the PLL. The LOCK bit is set when the VCO frequency is within a certain tolerance and is cleared when the VCO frequency is out of a certain tolerance. (See 7.8 Acquisition/Lock Time Specifications for more information.) CPU interrupts can occur if enabled (PLLIE = 1) when the PLL's lock condition changes, toggling the LOCK bit. (See 7.5.1 PLL Control Register.)
*
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* *
*
The PLL also may operate in manual mode (AUTO = 0). Manual mode is used by systems that do not require an indicator of the lock condition for proper operation. Such systems typically operate well below fBUSMAX. The following conditions apply when in manual mode: * * ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual mode, the ACQ bit must be clear. Before entering tracking mode (ACQ = 1), software must wait a given time, tACQ (See 7.8 Acquisition/Lock Time Specifications.), after turning on the PLL by setting PLLON in the PLL control register (PCTL). Software must wait a given time, tAL, after entering tracking mode before selecting the PLL as the clock source to CGMOUT (BCS = 1). The LOCK bit is disabled. CPU interrupts from the CGM are disabled.
* * *
MC68HC908GZ8 MOTOROLA Clock Generator Module (CGM)
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7.3.6 Programming the PLL Use the following procedure to program the PLL. For reference, the variables used and their meaning are shown in Table 7-1. Table 7-1. Variable Definitions
Variable fBUSDES fVCLKDES fRCLK Definition Desired bus clock frequency Desired VCO clock frequency Chosen reference crystal frequency Calculated VCO clock frequency Calculated bus clock frequency Nominal VCO center frequency Programmed VCO center frequency
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fVCLK fBUS fNOM fVRS
NOTE:
The round function in the following equations means that the real number should be rounded to the nearest integer number. 1. Choose the desired bus frequency, fBUSDES. 2. Calculate the desired VCO frequency (four times the desired bus frequency). fVCLKDES = 4 x fBUSDES 3. Choose a practical PLL (crystal) reference frequency, fRCLK. Typically, the reference crystal is 1-8 MHz. Frequency errors to the PLL are corrected at a rate of fRCLK. For stability and lock time reduction, this rate must be as fast as possible. The VCO frequency must be an integer multiple of this rate. The relationship between the VCO frequency, fVCLK, and the reference frequency, fRCLK, is: fVCLK = (N) (fRCLK) N, the range multiplier, must be an integer. In cases where desired bus frequency has some tolerance, choose fRCLK to a value determined either by other module requirements (such as modules which are clocked by CGMXCLK), cost requirements, or ideally, as high as the specified range allows. See Section 24. Electrical Specifications. After choosing N, the actual bus frequency can be determined using equation in 2 above. 4. Select a VCO frequency multiplier, N. f VCLKDES N = round ------------------------- f RCLK
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Clock Generator Module (CGM) Functional Description
5. Calculate and verify the adequacy of the VCO and bus frequencies fVCLK and fBUS. f VCLK = ( N ) x f RCLK f BUS = ( f VCLK ) 4 6. Select the VCO's power-of-two range multiplier E, according to Table 7-2. Table 7-2. Power-of-Two Range Selectors
Frequency Range 0 < fVCLK 8 MHz E 0 1 2(1)
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8 MHz< fVCLK 16 MHz 16 MHz< fVCLK 32 MHz 1. Do not program E to a value of 3.
7. Select a VCO linear range multiplier, L, where fNOM = 71.4 kHz fVCLK L = Round 2E x fNOM
8. Calculate and verify the adequacy of the VCO programmed center-of-range frequency, fVRS. The center-of-range frequency is the midpoint between the minimum and maximum frequencies attainable by the PLL. fVRS = (L x 2E) fNOM 9. For proper operation, f NOM x 2 f VRS - f VCLK -------------------------2
E
10. Verify the choice of N, E, and L by comparing fVCLK to fVRS and fVCLKDES. For proper operation, fVCLK must be within the application's tolerance of fVCLKDES, and fVRS must be as close as possible to fVCLK. NOTE: Exceeding the recommended maximum bus frequency or VCO frequency can crash the MCU. 11. Program the PLL registers accordingly: a. In the VPR bits of the PLL control register (PCTL), program the binary equivalent of E. b. In the PLL multiplier select register low (PMSL) and the PLL multiplier select register high (PMSH), program the binary equivalent of N. If using a 1-8 MHz reference, the PMSL register must be reprogrammed from the reset value before enabling the pll. c. In the PLL VCO range select register (PMRS), program the binary coded equivalent of L.
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Clock Generator Module (CGM)
Table 7-3 provides numeric examples (register values are in hexadecimal notation): Table 7-3. Numeric Example
fBUS 500 kHz 1.25 MHz 2.0 MHz 2.5 MHz 3.0 MHz fRCLK 1 MHz 1 MHz 1 MHz 1 MHz 1 MHz 1 MHz 1 MHz 1 MHz 1 MHz N 002 005 008 00A 00C 010 014 01C 020 E 0 0 0 1 1 1 2 2 2 L 1B 45 70 45 53 70 46 62 70
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4.0 MHz 5.0 MHz 7.0 MHz 8.0 MHz
7.3.7 Special Programming Exceptions The programming method described in 7.3.6 Programming the PLL does not account for two possible exceptions. A value of 0 for N or L is meaningless when used in the equations given. To account for these exceptions: * * A 0 value for N is interpreted exactly the same as a value of 1. A 0 value for L disables the PLL and prevents its selection as the source for the base clock.
See 7.3.8 Base Clock Selector Circuit. 7.3.8 Base Clock Selector Circuit This circuit is used to select either the crystal clock, CGMXCLK, or the VCO clock, CGMVCLK, as the source of the base clock, CGMOUT. The two input clocks go through a transition control circuit that waits up to three CGMXCLK cycles and three CGMVCLK cycles to change from one clock source to the other. During this time, CGMOUT is held in stasis. The output of the transition control circuit is then divided by two to correct the duty cycle. Therefore, the bus clock frequency, which is one-half of the base clock frequency, is one-fourth the frequency of the selected clock (CGMXCLK or CGMVCLK). The BCS bit in the PLL control register (PCTL) selects which clock drives CGMOUT. The VCO clock cannot be selected as the base clock source if the PLL is not turned on. The PLL cannot be turned off if the VCO clock is selected. The PLL cannot be turned on or off simultaneously with the selection or deselection of the VCO clock. The VCO clock also cannot be selected as the base clock source if the factor L is programmed to a 0. This value would set up a condition inconsistent with the operation of the PLL, so that the PLL would be disabled and the crystal clock would be forced as the source of the base clock.
Data Sheet 90 Clock Generator Module (CGM) MC68HC908GZ8 MOTOROLA
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Clock Generator Module (CGM) Functional Description
7.3.9 CGM External Connections In its typical configuration, the CGM requires external components. Five of these are for the crystal oscillator and two or four are for the PLL. The crystal oscillator is normally connected in a Pierce oscillator configuration, as shown in Figure 7-2. Figure 7-2 shows only the logical representation of the internal components and may not represent actual circuitry. The oscillator configuration uses five components: * Crystal, X1 * Fixed capacitor, C1 * Tuning capacitor, C2 (can also be a fixed capacitor) * Feedback resistor, RB * Series resistor, RS The series resistor (RS) is included in the diagram to follow strict Pierce oscillator guidelines. Refer to the crystal manufacturer's data for more information regarding values for C1 and C2. Figure 7-2 also shows the external components for the PLL: * Bypass capacitor, CBYP * Filter network Routing should be done with great care to minimize signal cross talk and noise.
SIMOSCEN OSCSTOPENB (FROM CONFIG)
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CGMXCLK
OSC1
OSC2
CGMXFC
VSSA
VDDA VDD
RB RF1 RS CF1 X1 C1 C2 3 Component Filter CF2 CBYP 0.1 F
Note: Filter network in box can be replaced with a single capacitor, but will degrade stability.
Figure 7-2. CGM External Connections
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7.4 I/O Signals
The following paragraphs describe the CGM I/O signals. 7.4.1 Crystal Amplifier Input Pin (OSC1) The OSC1 pin is an input to the crystal oscillator amplifier. 7.4.2 Crystal Amplifier Output Pin (OSC2) The OSC2 pin is the output of the crystal oscillator inverting amplifier.
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7.4.3 External Filter Capacitor Pin (CGMXFC) The CGMXFC pin is required by the loop filter to filter out phase corrections. An external filter network is connected to this pin. (See Figure 7-2.) NOTE: To prevent noise problems, the filter network should be placed as close to the CGMXFC pin as possible, with minimum routing distances and no routing of other signals across the network.
7.4.4 PLL Analog Power Pin (VDDA) VDDA is a power pin used by the analog portions of the PLL. Connect the VDDA pin to the same voltage potential as the VDD pin. NOTE: Route VDDA carefully for maximum noise immunity and place bypass capacitors as close as possible to the package.
7.4.5 PLL Analog Ground Pin (VSSA) VSSA is a ground pin used by the analog portions of the PLL. Connect the VSSA pin to the same voltage potential as the VSS pin. NOTE: Route VSSA carefully for maximum noise immunity and place bypass capacitors as close as possible to the package.
7.4.6 Oscillator Enable Signal (SIMOSCEN) The SIMOSCEN signal comes from the system integration module (SIM) and enables the oscillator and PLL. 7.4.7 Oscillator Stop Mode Enable Bit (OSCSTOPENB) OSCSTOPENB is a bit in the CONFIG register that enables the oscillator to continue operating during stop mode. If this bit is set, the Oscillator continues running during stop mode. If this bit is not set (default), the oscillator is controlled by the SIMOSCEN signal which will disable the oscillator during stop mode.
Data Sheet 92 Clock Generator Module (CGM)
MC68HC908GZ8 MOTOROLA
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Clock Generator Module (CGM) CGM Registers
7.4.8 Crystal Output Frequency Signal (CGMXCLK) CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (fXCLK) and comes directly from the crystal oscillator circuit. Figure 7-2 shows only the logical relation of CGMXCLK to OSC1 and OSC2 and may not represent the actual circuitry. The duty cycle of CGMXCLK is unknown and may depend on the crystal and other external factors. Also, the frequency and amplitude of CGMXCLK can be unstable at start up. 7.4.9 CGM Base Clock Output (CGMOUT)
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CGMOUT is the clock output of the CGM. This signal goes to the SIM, which generates the MCU clocks. CGMOUT is a 50 percent duty cycle clock running at twice the bus frequency. CGMOUT is software programmable to be either the oscillator output, CGMXCLK, divided by two or the VCO clock, CGMVCLK, divided by two. 7.4.10 CGM CPU Interrupt (CGMINT) CGMINT is the interrupt signal generated by the PLL lock detector.
7.5 CGM Registers
These registers control and monitor operation of the CGM: * * * * * PLL control register (PCTL) (See 7.5.1 PLL Control Register.) PLL bandwidth control register (PBWC) (See 7.5.2 PLL Bandwidth Control Register.) PLL multiplier select register high (PMSH) (See 7.5.3 PLL Multiplier Select Register High.) PLL multiplier select register low (PMSL) (See 7.5.4 PLL Multiplier Select Register Low.) PLL VCO range select register (PMRS) (See 7.5.5 PLL VCO Range Select Register.)
Figure 7-3 is a summary of the CGM registers.
MC68HC908GZ8 MOTOROLA Clock Generator Module (CGM)
Data Sheet 93
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Clock Generator Module (CGM)
Addr. $0036
Register Name PLL Control Register Read: (PCTL) Write: See page 94. Reset:
Bit 7 PLLIE 0 AUTO 0 0 0 MUL7 0 VRS7 0 0 0
6 PLLF 0 LOCK 0 0 0 MUL6 1 VRS6 1 0 0 = Unimplemented
5 PLLON 1 ACQ 0 0 0 MUL5 0 VRS5 0 0 0
4 BCS 0 0 0 0 0 MUL4 0 VRS4 0 0 0 R
3 R 0 0 0 MUL11 0 MUL3 0 VRS3 0 R 0 = Reserved
2 R 0 0 0 MUL10 0 MUL2 0 VRS2 0 R 0
1 VPR1 0 0 0 MUL9 0 MUL1 0 VRS1 0 R 0
Bit 0 VPR0 0 R 0 MUL8 0 MUL0 0 VRS0 0 R 1
PLL Bandwidth Control Reg- Read: $0037 ister (PBWC) Write: See page 96. Reset: $0038 PLL Multiplier Select High Read: Register (PMSH) Write: See page 97. Reset: PLL Multiplier Select Low Read: Register (PMSL) Write: See page 98. Reset: PLL VCO Select Range Read: Register (PMRS) Write: See page 98. Reset: Read: $003B Reserved Register Write: Reset:
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$0039
$003A
NOTES: 1. When AUTO = 0, PLLIE is forced clear and is read-only. 2. When AUTO = 0, PLLF and LOCK read as clear. 3. When AUTO = 1, ACQ is read-only. 4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only. 5. When PLLON = 1, the PLL programming register is read-only. 6. When BCS = 1, PLLON is forced set and is read-only.
Figure 7-3. CGM I/O Register Summary 7.5.1 PLL Control Register The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, the base clock selector bit, and the VCO power-of-two range selector bits.
Address: $0036 Bit 7 Read: PLLIE Write: Reset: 0 0 = Unimplemented 1 0 0 R 0 = Reserved 0 0 6 PLLF PLLON BCS R R VPR1 VPR0 5 4 3 2 1 Bit 0
Figure 7-4. PLL Control Register (PCTL)
Data Sheet 94 Clock Generator Module (CGM) MC68HC908GZ8 MOTOROLA
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Clock Generator Module (CGM) CGM Registers
PLLIE -- PLL Interrupt Enable Bit This read/write bit enables the PLL to generate an interrupt request when the LOCK bit toggles, setting the PLL flag, PLLF. When the AUTO bit in the PLL bandwidth control register (PBWC) is clear, PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE bit. 1 = PLL interrupts enabled 0 = PLL interrupts disabled PLLF -- PLL Interrupt Flag Bit This read-only bit is set whenever the LOCK bit toggles. PLLF generates an interrupt request if the PLLIE bit also is set. PLLF always reads as logic 0 when the AUTO bit in the PLL bandwidth control register (PBWC) is clear. Clear the PLLF bit by reading the PLL control register. Reset clears the PLLF bit. 1 = Change in lock condition 0 = No change in lock condition NOTE: Do not inadvertently clear the PLLF bit. Any read or read-modify-write operation on the PLL control register clears the PLLF bit. PLLON -- PLL On Bit This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). (See 7.3.8 Base Clock Selector Circuit.) Reset sets this bit so that the loop can stabilize as the MCU is powering up. 1 = PLL on 0 = PLL off BCS -- Base Clock Select Bit This read/write bit selects either the crystal oscillator output, CGMXCLK, or the VCO clock, CGMVCLK, as the source of the CGM output, CGMOUT. CGMOUT frequency is one-half the frequency of the selected clock. BCS cannot be set while the PLLON bit is clear. After toggling BCS, it may take up to three CGMXCLK and three CGMVCLK cycles to complete the transition from one source clock to the other. During the transition, CGMOUT is held in stasis. (See 7.3.8 Base Clock Selector Circuit.) Reset clears the BCS bit. 1 = CGMVCLK divided by two drives CGMOUT 0 = CGMXCLK divided by two drives CGMOUT NOTE: PLLON and BCS have built-in protection that prevents the base clock selector circuit from selecting the VCO clock as the source of the base clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0), selecting CGMVCLK requires two writes to the PLL control register. (See 7.3.8 Base Clock Selector Circuit.). VPR1 and VPR0 -- VCO Power-of-Two Range Select Bits These read/write bits control the VCO's hardware power-of-two range multiplier E that, in conjunction with L controls the hardware center-of-range frequency, fVRS. VPR1:VPR0 cannot be written when the PLLON bit is set. Reset clears
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MC68HC908GZ8 MOTOROLA Clock Generator Module (CGM)
Data Sheet 95
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these bits. (See 7.3.3 PLL Circuits, 7.3.6 Programming the PLL, and 7.5.5 PLL VCO Range Select Register.) Table 7-4. VPR1 and VPR0 Programming
VPR1 and VPR0 00 01 10 E 0 1 2(1) VCO Power-of-Two Range Multiplier 1 2 4
1. Do not program E to a value of 3.
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NOTE:
Verify that the value of the VPR1 and VPR0 bits in the PCTL register are appropriate for the given reference and VCO clock frequencies before enabling the PLL. See 7.3.6 Programming the PLL for detailed instructions on selecting the proper value for these control bits.
7.5.2 PLL Bandwidth Control Register The PLL bandwidth control register (PBWC): * * * * Selects automatic or manual (software-controlled) bandwidth control mode Indicates when the PLL is locked In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode In manual operation, forces the PLL into acquisition or tracking mode
Address: $0037 Bit 7 Read: Write: Reset: AUTO 0 6 LOCK 0 = Unimplemented 5 ACQ 0 4 0 0 R 3 0 0 = Reserved 2 0 0 1 0 0 Bit 0 R 0
Figure 7-5. PLL Bandwidth Control Register (PBWC) AUTO -- Automatic Bandwidth Control Bit This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual operation (AUTO = 0), clear the ACQ bit before turning on the PLL. Reset clears the AUTO bit. 1 = Automatic bandwidth control 0 = Manual bandwidth control LOCK -- Lock Indicator Bit When the AUTO bit is set, LOCK is a read-only bit that becomes set when the VCO clock, CGMVCLK, is locked (running at the programmed frequency).
Data Sheet 96 Clock Generator Module (CGM)
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Clock Generator Module (CGM) CGM Registers
When the AUTO bit is clear, LOCK reads as logic 0 and has no meaning. The write one function of this bit is reserved for test, so this bit must always be written a 0. Reset clears the LOCK bit. 1 = VCO frequency correct or locked 0 = VCO frequency incorrect or unlocked ACQ -- Acquisition Mode Bit When the AUTO bit is set, ACQ is a read-only bit that indicates whether the PLL is in acquisition mode or tracking mode. When the AUTO bit is clear, ACQ is a read/write bit that controls whether the PLL is in acquisition or tracking mode. In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit, enabling acquisition mode. 1 = Tracking mode 0 = Acquisition mode 7.5.3 PLL Multiplier Select Register High The PLL multiplier select register high (PMSH) contains the programming information for the high byte of the modulo feedback divider.
Address: $0038 Bit 7 Read: Write: Reset: 0 0 = Unimplemented 0 0 0 0 0 0 0 6 0 5 0 4 0 MUL11 MUL10 MUL9 MUL8 3 2 1 Bit 0
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Figure 7-6. PLL Multiplier Select Register High (PMSH) MUL11-MUL8 -- Multiplier Select Bits These read/write bits control the high byte of the modulo feedback divider that selects the VCO frequency multiplier N. (See 7.3.3 PLL Circuits and 7.3.6 Programming the PLL.) A value of $0000 in the multiplier select registers configures the modulo feedback divider the same as a value of $0001. Reset initializes the registers to $0040 for a default multiply value of 64. NOTE: The multiplier select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1). PMSH[7:4] -- Unimplemented Bits These bits have no function and always read as logic 0s.
MC68HC908GZ8 MOTOROLA Clock Generator Module (CGM)
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7.5.4 PLL Multiplier Select Register Low The PLL multiplier select register low (PMSL) contains the programming information for the low byte of the modulo feedback divider.
Address: Read: Write: Reset: $0038 Bit 7 MUL7 0 6 MUL6 1 5 MUL5 0 4 MUL4 0 3 MUL3 0 2 MUL2 0 1 MUL1 0 Bit 0 MUL0 0
Figure 7-7. PLL Multiplier Select Register Low (PMSL)
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NOTE:
For applications using 1-8 MHz reference frequencies this register must be reprogrammed before enabling the PLL. The reset value of this register will cause applications using 1-8 MHz reference frequencies to become unstable if the PLL is enabled without programming an appropriate value. The programmed value must not allow the VCO clock to exceed 32 MHz. See 7.3.6 Programming the PLL for detailed instructions on choosing the proper value for PMSL. MUL7-MUL0 -- Multiplier Select Bits These read/write bits control the low byte of the modulo feedback divider that selects the VCO frequency multiplier, N. (See 7.3.3 PLL Circuits and 7.3.6 Programming the PLL.) MUL7-MUL0 cannot be written when the PLLON bit in the PCTL is set. A value of $0000 in the multiplier select registers configures the modulo feedback divider the same as a value of $0001. Reset initializes the register to $40 for a default multiply value of 64.
NOTE:
The multiplier select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1).
7.5.5 PLL VCO Range Select Register NOTE: PMRS may be called PVRS on other HC08 derivatives. The PLL VCO range select register (PMRS) contains the programming information required for the hardware configuration of the VCO.
Address: Read: Write: Reset: $003A Bit 7 VRS7 0 6 VRS6 1 5 VRS5 0 4 VRS4 0 3 VRS3 0 2 VRS2 0 1 VRS1 0 Bit 0 VRS0 0
Figure 7-8. PLL VCO Range Select Register (PMRS) NOTE: Verify that the value of the PMRS register is appropriate for the given reference and VCO clock frequencies before enabling the PLL. See 7.3.6 Programming the PLL for detailed instructions on selecting the proper value for these control bits.
MC68HC908GZ8 Clock Generator Module (CGM) MOTOROLA
Data Sheet 98
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Clock Generator Module (CGM) Interrupts
VRS7-VRS0 -- VCO Range Select Bits These read/write bits control the hardware center-of-range linear multiplier L which, in conjunction with E (See 7.3.3 PLL Circuits, 7.3.6 Programming the PLL, and 7.5.1 PLL Control Register.), controls the hardware center-of-range frequency, fVRS. VRS7-VRS0 cannot be written when the PLLON bit in the PCTL is set. (See 7.3.7 Special Programming Exceptions.) A value of $00 in the VCO range select register disables the PLL and clears the BCS bit in the PLL control register (PCTL). (See 7.3.8 Base Clock Selector Circuit and 7.3.7 Special Programming Exceptions.). Reset initializes the register to $40 for a default range multiply value of 64. NOTE:
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The VCO range select bits have built-in protection such that they cannot be written when the PLL is on (PLLON = 1) and such that the VCO clock cannot be selected as the source of the base clock (BCS = 1) if the VCO range select bits are all clear. The PLL VCO range select register must be programmed correctly. Incorrect programming can result in failure of the PLL to achieve lock.
7.6 Interrupts
When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL) enables CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether interrupts are enabled or not. When the AUTO bit is clear, CPU interrupts from the PLL are disabled and PLLF reads as logic 0. Software should read the LOCK bit after a PLL interrupt request to see if the request was due to an entry into lock or an exit from lock. When the PLL enters lock, the VCO clock, CGMVCLK, divided by two can be selected as the CGMOUT source by setting BCS in the PCTL. When the PLL exits lock, the VCO clock frequency is corrupt, and appropriate precautions should be taken. If the application is not frequency sensitive, interrupts should be disabled to prevent PLL interrupt service routines from impeding software performance or from exceeding stack limitations. NOTE: Software can select the CGMVCLK divided by two as the CGMOUT source even if the PLL is not locked (LOCK = 0). Therefore, software should make sure the PLL is locked before setting the BCS bit.
7.7 Special Modes
The WAIT instruction puts the MCU in low power-consumption standby modes. 7.7.1 Wait Mode The WAIT instruction does not affect the CGM. Before entering wait mode, software can disengage and turn off the PLL by clearing the BCS and PLLON bits
MC68HC908GZ8 MOTOROLA Clock Generator Module (CGM) Data Sheet 99
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Clock Generator Module (CGM)
in the PLL control register (PCTL) to save power. Less power-sensitive applications can disengage the PLL without turning it off, so that the PLL clock is immediately available at WAIT exit. This would be the case also when the PLL is to wake the MCU from wait mode, such as when the PLL is first enabled and waiting for LOCK or LOCK is lost. 7.7.2 Stop Mode If the OSCSTOPENB bit in the CONFIG register is cleared (default), then the STOP instruction disables the CGM (oscillator and phase locked loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and CGMINT).
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If the OSCSTOPENB bit in the CONFIG register is set, then the phase locked loop is shut off but the oscillator will continue to operate in stop mode. 7.7.3 CGM During Break Interrupts The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. (See 20.7.3 Break Flag Control Register.) To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the PLLF bit during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write the PLL control register during the break state without affecting the PLLF bit.
7.8 Acquisition/Lock Time Specifications
The acquisition and lock times of the PLL are, in many applications, the most critical PLL design parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock times. 7.8.1 Acquisition/Lock Time Definitions Typical control systems refer to the acquisition time or lock time as the reaction time, within specified tolerances, of the system to a step input. In a PLL, the step input occurs when the PLL is turned on or when it suffers a noise hit. The tolerance is usually specified as a percent of the step input or when the output settles to the desired value plus or minus a percent of the frequency change. Therefore, the reaction time is constant in this definition, regardless of the size of the step input. For example, consider a system with a 5 percent acquisition time tolerance. If a command instructs the system to change from 0 Hz to 1 MHz, the acquisition time is the time taken for the frequency to reach 1 MHz 50 kHz. Fifty kHz = 5% of the 1-MHz step input. If the system is operating at 1 MHz and suffers a -100-kHz noise
Data Sheet 100 Clock Generator Module (CGM) MC68HC908GZ8 MOTOROLA
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Clock Generator Module (CGM) Acquisition/Lock Time Specifications
hit, the acquisition time is the time taken to return from 900 kHz to 1 MHz 5 kHz. Five kHz = 5% of the 100-kHz step input. Other systems refer to acquisition and lock times as the time the system takes to reduce the error between the actual output and the desired output to within specified tolerances. Therefore, the acquisition or lock time varies according to the original error in the output. Minor errors may not even be registered. Typical PLL applications prefer to use this definition because the system requires the output frequency to be within a certain tolerance of the desired frequency regardless of the size of the initial error. 7.8.2 Parametric Influences on Reaction Time
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Acquisition and lock times are designed to be as short as possible while still providing the highest possible stability. These reaction times are not constant, however. Many factors directly and indirectly affect the acquisition time. The most critical parameter which affects the reaction times of the PLL is the reference frequency, fRCLK. This frequency is the input to the phase detector and controls how often the PLL makes corrections. For stability, the corrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error. Therefore, the slower the reference the longer it takes to make these corrections. This parameter is under user control via the choice of crystal frequency fXCLK. (See 7.3.3 PLL Circuits and 7.3.6 Programming the PLL.) Another critical parameter is the external filter network. The PLL modifies the voltage on the VCO by adding or subtracting charge from capacitors in this network. Therefore, the rate at which the voltage changes for a given frequency error (thus change in charge) is proportional to the capacitance. The size of the capacitor also is related to the stability of the PLL. If the capacitor is too small, the PLL cannot make small enough adjustments to the voltage and the system cannot lock. If the capacitor is too large, the PLL may not be able to adjust the voltage in a reasonable time. (See 7.8.3 Choosing a Filter.) Also important is the operating voltage potential applied to VDDA. The power supply potential alters the characteristics of the PLL. A fixed value is best. Variable supplies, such as batteries, are acceptable if they vary within a known range at very slow speeds. Noise on the power supply is not acceptable, because it causes small frequency errors which continually change the acquisition time of the PLL. Temperature and processing also can affect acquisition time because the electrical characteristics of the PLL change. The part operates as specified as long as these influences stay within the specified limits. External factors, however, can cause drastic changes in the operation of the PLL. These factors include noise injected into the PLL through the filter capacitor, filter capacitor leakage, stray impedances on the circuit board, and even humidity or circuit board contamination.
MC68HC908GZ8 MOTOROLA Clock Generator Module (CGM)
Data Sheet 101
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Clock Generator Module (CGM)
7.8.3 Choosing a Filter As described in 7.8.2 Parametric Influences on Reaction Time, the external filter network is critical to the stability and reaction time of the PLL. The PLL is also dependent on reference frequency and supply voltage. Figure 7-9 shows two types of filter circuits. In low-cost applications, where stability and reaction time of the PLL are not critical, the three component filter network shown in Figure 7-9 (B) can be replaced by a single capacitor, CF, as shown in shown in Figure 7-9 (A). Refer to Table 7-5 for recommended filter components at various reference frequencies. For reference frequencies between the values listed in the table, extrapolate to the nearest common capacitor value. In general, a slightly larger capacitor provides more stability at the expense of increased lock time.
CGMXFC CGMXFC
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RF1 CF CF1
CF2
VSSA
VSSA
(A)
(B)
Figure 7-9. PLL Filter Table 7-5. Example Filter Component Values
fRCLK 1 MHz 2 MHz 3 MHz 4 MHz 5 MHz 6 MHz 7 MHz 8 MHz CF1 8.2 nF 4.7 nF 3.3 nF 2.2 nF 1.8 nF 1.5 nF 1.2 nF 1 nF CF2 820 pF 470 pF 330 pF 220 pF 180 pF 150 pF 120 pF 100 pF RF1 2k 2k 2k 2k 2k 2k 2k 2k CF 18 nF 6.8 nF 5.6 nF 4.7 nF 3.9 nF 3.3 nF 2.7 nF 2.2 nF
Data Sheet 102 Clock Generator Module (CGM)
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Section 8. Configuration Register (CONFIG)
8.1 Introduction
This section describes the configuration registers, CONFIG1 and CONFIG2. The configuration registers enable or disable these options:
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* * * * * * * *
Stop mode recovery time (32 CGMXCLK cycles or 4096 CGMXCLK cycles) COP timeout period (218 - 24 or 213 - 24 COPCLK cycles) STOP instruction Computer operating properly module (COP) Low-voltage inhibit (LVI) module control and voltage trip point selection Enable/disable the oscillator (OSC) during stop mode Enable/disable an extra divide by 128 prescaler in timebase module Enable for Motorola scalable controller area network (MSCAN)
8.2 Functional Description
The configuration registers are used in the initialization of various options. The configuration registers can be written once after each reset. All of the configuration register bits are cleared during reset. Since the various options affect the operation of the microcontroller unit (MCU), it is recommended that these registers be written immediately after reset. The configuration registers are located at $001E and $001F and may be read at anytime. NOTE: On a FLASH device, the options except LVI5OR3 are one-time writable by the user after each reset. The LVI5OR3 bit is one-time writable by the user only after each POR (power-on reset). The CONFIG registers are not in the FLASH memory but are special registers containing one-time writable latches after each reset. Upon a reset, the CONFIG registers default to predetermined settings as shown in Figure 8-1 and Figure 8-2.
MC68HC908GZ8 MOTOROLA Configuration Register (CONFIG)
Data Sheet 103
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Configuration Register (CONFIG)
Address: Read: Write: Reset:
$001E Bit 7 0 0 6 0 0 = Unimplemented 5 0 0 4 0 0 3 2 1 Bit 0
MSCAN-EN TMCLKSEL See note 0
OSCEN-INSCIBDSRC STOP 0 1
Note: MSCANEN is only reset via POR (power-on reset).
Figure 8-1. Configuration Register 2 (CONFIG2)
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Address: Read: Write: Reset:
$001F Bit 7 COPRS 0 6 LVISTOP 0 5 LVIRSTD 0 4 LVIPWRD 0 3 LVI5OR3 See note 2 SSREC 0 1 STOP 0 Bit 0 COPD 0
Note: LVI5OR3 is only reset via POR (power-on reset).
Figure 8-2. Configuration Register 1 (CONFIG1) MSCANEN-- MSCAN08 Enable Bit Setting the MSCANEN enables the MSCAN08 module and allows the MSCAN08 to use the PTC0/PTC1 pins. See Section 16. MSCAN08 Controller (MSCAN08) for a more detailed description of the MSCAN08 operation. 1 = Enables MSCAN08 module 0 = Disables the MSCAN08 module NOTE: The MSCANEN bit is cleared by a power-on reset (POR) only. Other resets will leave this bit unaffected. TMCLKSEL-- Timebase Clock Select Bit TMCLKSEL enables an extra divide-by-128 prescaler in the timebase module. Setting this bit enables the extra prescaler and clearing this bit disables it. See Section 7. Clock Generator Module (CGM) for a more detailed description of the external clock operation. 1 = Enables extra divide-by-128 prescaler in timebase module 0 = Disables extra divide-by-128 prescaler in timebase module OSCENINSTOP -- Oscillator Enable In Stop Mode Bit OSCENINSTOP, when set, will enable the oscillator to continue to generate clocks in stop mode. See Section 7. Clock Generator Module (CGM). This function is used to keep the timebase running while the reset of the MCU stops. See Section 22. Timebase Module (TBM). When clear, oscillator will cease to generate clocks while in stop mode. The default state for this option is clear, disabling the oscillator in stop mode. 1 = Oscillator enabled to operate during stop mode 0 = Oscillator disabled during stop mode (default)
Data Sheet 104 Configuration Register (CONFIG) MC68HC908GZ8 MOTOROLA
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Configuration Register (CONFIG) Functional Description
SCIBDSRC -- SCI Baud Rate Clock Source Bit SCIBDSRC controls the clock source used for the serial communications interface (SCI). The setting of this bit affects the frequency at which the SCI operates.See Section 19. Enhanced Serial Communications Interface (ESCI) Module. 1 = Internal data bus clock used as clock source for SCI (default) 0 = External oscillator used as clock source for SCI COPRS -- COP Rate Select Bit COPD selects the COP timeout period. Reset clears COPRS. See Section 9. Computer Operating Properly (COP) Module 1 = COP timeout period = 213 - 24 COPCLK cycles 0 = COP timeout period = 218 - 24 COPCLK cycles LVISTOP -- LVI Enable in Stop Mode Bit When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode. Reset clears LVISTOP. 1 = LVI enabled during stop mode 0 = LVI disabled during stop mode LVIRSTD -- LVI Reset Disable Bit LVIRSTD disables the reset signal from the LVI module. See Section 14. Low-Voltage Inhibit (LVI). 1 = LVI module resets disabled 0 = LVI module resets enabled LVIPWRD -- LVI Power Disable Bit LVIPWRD disables the LVI module. See Section 14. Low-Voltage Inhibit (LVI). 1 = LVI module power disabled 0 = LVI module power enabled LVI5OR3 -- LVI 5-V or 3-V Operating Mode Bit LVI5OR3 selects the voltage operating mode of the LVI module (see Section 14. Low-Voltage Inhibit (LVI)). The voltage mode selected for the LVI should match the operating VDD (see Section 24. Electrical Specifications) for the LVI's voltage trip points for each of the modes. 1 = LVI operates in 5-V mode 0 = LVI operates in 3-V mode NOTE: The LVI5OR3 bit is cleared by a power-on reset (POR) only. Other resets will leave this bit unaffected. SSREC -- Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a 4096-CGMXCLK cycle delay. 1 = Stop mode recovery after 32 CGMXCLK cycles 0 = Stop mode recovery after 4096 CGMXCLCK cycles NOTE: Exiting stop mode by an LVI reset will result in the long stop recovery.
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MC68HC908GZ8 MOTOROLA
Data Sheet Configuration Register (CONFIG) 105
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Configuration Register (CONFIG)
If the system clock source selected is the internal oscillator or the external crystal and the OSCENINSTOP configuration bit is not set, the oscillator will be disabled during stop mode. The short stop recovery does not provide enough time for oscillator stabilization and for this reason the SSREC bit should not be set. When using the LVI during normal operation but disabling during stop mode, the LVI will have an enable time of tEN. The system stabilization time for power-on reset and long stop recovery (both 4096 CGMXCLK cycles) gives a delay longer than the LVI enable time for these startup scenarios. There is no period where the MCU is not protected from a low-power condition. However, when using the short stop recovery configuration option, the 32-CGMXCLK delay must be greater than the LVI's turn on time to avoid a period in startup where the LVI is not protecting the MCU. STOP -- STOP Instruction Enable Bit STOP enables the STOP instruction. 1 = STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD -- COP Disable Bit COPD disables the COP module. See Section 9. Computer Operating Properly (COP) Module. 1 = COP module disabled 0 = COP module enabled
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Data Sheet 106
MC68HC908GZ8 Configuration Register (CONFIG) MOTOROLA
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Data Sheet -- MC68HC908GZ8
Section 9. Computer Operating Properly (COP) Module
9.1 Introduction
The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the CONFIG register.
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9.2 Functional Description
Figure 9-1 shows the structure of the COP module.
CGMXCLK
12-BIT COP PRESCALER CLEAR STAGES 5-12 CLEAR ALL STAGES
RESET CIRCUIT RESET STATUS REGISTER
STOP INSTRUCTION INTERNAL RESET SOURCES RESET VECTOR FETCH COPCTL WRITE
COP CLOCK COP MODULE 6-BIT COP COUNTER COPEN (FROM SIM) COP DISABLE (FROM CONFIG) RESET COPCTL WRITE COP RATE SEL (FROM CONFIG)
CLEAR COP COUNTER
Figure 9-1. COP Block Diagram
MC68HC908GZ8 MOTOROLA Computer Operating Properly (COP) Module
COP TIMEOUT
Data Sheet 107
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Computer Operating Properly (COP) Module
The COP counter is a free-running 6-bit counter preceded by a 12-bit prescaler counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 218 - 24 or 213 - 24 CGMXCLK cycles, depending on the state of the COP rate select bit, COPRS, in the configuration register. With a 213 - 24 CGMXCLK cycle overflow option, a 4.9152-MHz crystal gives a COP timeout period of 53.3 ms. Writing any value to location $FFFF before an overflow occurs prevents a COP reset by clearing the COP counter and stages 12-5 of the prescaler. NOTE: Service the COP immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first COP counter overflow. A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the COP bit in the reset status register (RSR). In monitor mode, the COP is disabled if the RST pin or the IRQ1 is held at VTST. During the break state, VTST on the RST pin disables the COP. NOTE: Place COP clearing instructions in the main program and not in an interrupt subroutine. Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly.
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9.3 I/O Signals
The following paragraphs describe the signals shown in Figure 9-1. 9.3.1 CGMXCLK CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency is equal to the crystal frequency.
9.3.2 STOP Instruction The STOP instruction clears the COP prescaler. 9.3.3 COPCTL Write Writing any value to the COP control register (COPCTL) clears the COP counter and clears bits 12-5 of the prescaler. Reading the COP control register returns the low byte of the reset vector. See 9.4 COP Control Register. 9.3.4 Power-On Reset The power-on reset (POR) circuit clears the COP prescaler 4096 CGMXCLK cycles after power-up.
Data Sheet 108 Computer Operating Properly (COP) Module
MC68HC908GZ8 MOTOROLA
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Computer Operating Properly (COP) Module COP Control Register
9.3.5 Internal Reset An internal reset clears the COP prescaler and the COP counter. 9.3.6 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the COP prescaler. 9.3.7 COPD (COP Disable) The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. See Section 8. Configuration Register (CONFIG). 9.3.8 COPRS (COP Rate Select) The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register. See Section 8. Configuration Register (CONFIG).
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9.4 COP Control Register
The COP control register (COPCTL) is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector.
Address: $FFFF Bit 7 Read: Write: Reset: 6 5 4 3 2 1 Bit 0
Low byte of reset vector Clear COP counter Unaffected by reset
Figure 9-2. COP Control Register (COPCTL)
9.5 Interrupts
The COP does not generate central processor unit (CPU) interrupt requests.
9.6 Monitor Mode
When monitor mode is entered with VTST on the IRQ pin, the COP is disabled as long as VTST remains on the IRQ pin or the RST pin. When monitor mode is entered by having blank reset vectors and not having VTST on the IRQ pin, the COP is automatically disabled until a POR occurs.
MC68HC908GZ8 MOTOROLA Computer Operating Properly (COP) Module
Data Sheet 109
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Computer Operating Properly (COP) Module
9.7 Low-Power Modes
The WAIT and STOP instructions put the microcontroller unit (MCU) in low power-consumption standby modes. 9.7.1 Wait Mode The COP remains active during wait mode. If COP is enabled, a reset will occur at COP timeout. 9.7.2 Stop Mode
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Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode. To prevent inadvertently turning off the COP with a STOP instruction, a configuration option is available that disables the STOP instruction. When the STOP bit in the configuration register has the STOP instruction disabled, execution of a STOP instruction results in an illegal opcode reset.
9.8 COP Module During Break Mode
The COP is disabled during a break interrupt when VTST is present on the RST pin.
Data Sheet 110 Computer Operating Properly (COP) Module
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Data Sheet -- MC68HC908GZ8
Section 10. Central Processor Unit (CPU)
10.1 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Motorola document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture.
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10.2 Features
Features of the CPU include: * * * * * * * * * * * Object code fully upward-compatible with M68HC05 Family 16-bit stack pointer with stack manipulation instructions 16-bit index register with x-register manipulation instructions 8-MHz CPU internal bus frequency 64-Kbyte program/data memory space 16 addressing modes Memory-to-memory data moves without using accumulator Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions Enhanced binary-coded decimal (BCD) data handling Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes Low-power stop and wait modes
MC68HC908GZ8 MOTOROLA Central Processor Unit (CPU)
Data Sheet 111
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Central Processor Unit (CPU)
10.3 CPU Registers
Figure 10-1 shows the five CPU registers. CPU registers are not part of the memory map.
7 15 H 15 15 X 0 STACK POINTER (SP) 0 PROGRAM COUNTER (PC) 7 0 V11HINZC CONDITION CODE REGISTER (CCR) 0 ACCUMULATOR (A) 0 INDEX REGISTER (H:X)
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CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO'S COMPLEMENT OVERFLOW FLAG
Figure 10-1. CPU Registers 10.3.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
Bit 7 Read: Write: Reset: Unaffected by reset 6 5 4 3 2 1 Bit 0
Figure 10-2. Accumulator (A)
Data Sheet 112 Central Processor Unit (CPU)
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Central Processor Unit (CPU) CPU Registers
10.3.2 Index Register The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register. In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand. The index register can serve also as a temporary data storage location.
Bit 15 Read: Write: Reset: 0 0 0 0 0 0 0 0 X X X X X X X X Bit 0
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14
13
12
11
10
9
8
7
6
5
4
3
2
1
X = Indeterminate
Figure 10-3. Index Register (H:X) 10.3.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. The CPU uses the contents of the stack pointer to determine the conditional address of the operand.
Bit 15 Read: Write: Reset: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Figure 10-4. Stack Pointer (SP) NOTE: The location of the stack is arbitrary and may be relocated anywhere in random-access memory (RAM). Moving the SP out of page 0 ($0000 to $00FF) frees direct address (page 0) space. For correct operation, the stack pointer must point only to RAM locations.
MC68HC908GZ8 MOTOROLA Central Processor Unit (CPU)
Data Sheet 113
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Central Processor Unit (CPU)
10.3.4 Program Counter The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state.
Bit 15 Read: Write: Reset: Loaded with vector from $FFFE and $FFFF Bit 0
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14
13
12
11
10
9
8
7
6
5
4
3
2
1
Figure 10-5. Program Counter (PC) 10.3.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to logic 1. The following paragraphs describe the functions of the condition code register.
Bit 7 Read: V Write: Reset: X X = Indeterminate 1 1 X 1 X X X 1 1 H I N Z C 6 5 4 3 2 1 Bit 0
Figure 10-6. Condition Code Register (CCR) V -- Overflow Flag The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag. 1 = Overflow 0 = No overflow
Data Sheet 114 Central Processor Unit (CPU)
MC68HC908GZ8 MOTOROLA
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Central Processor Unit (CPU) CPU Registers
H -- Half-Carry Flag The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor. 1 = Carry between bits 3 and 4 0 = No carry between bits 3 and 4 I -- Interrupt Mask When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched. 1 = Interrupts disabled 0 = Interrupts enabled NOTE: To maintain M6805 Family compatibility, the upper byte of the index register (H) is not stacked automatically. If the interrupt service routine modifies H, then the user must stack and unstack H using the PSHH and PULH instructions. After the I bit is cleared, the highest-priority interrupt request is serviced first. A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (CLI). N -- Negative flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = Negative result 0 = Non-negative result Z -- Zero flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result C -- Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions -- such as bit test and branch, shift, and rotate -- also clear or set the carry/borrow flag. 1 = Carry out of bit 7 0 = No carry out of bit 7
Freescale Semiconductor, Inc...
MC68HC908GZ8 MOTOROLA Central Processor Unit (CPU)
Data Sheet 115
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Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
10.4 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the instruction set. Refer to the CPU08 Reference Manual (Motorola document order number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about the architecture of the CPU.
10.5 Low-Power Modes
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The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 10.5.1 Wait Mode The WAIT instruction: * Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock
* 10.5.2 Stop Mode
The STOP instruction: * Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock
*
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
10.6 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break interrupt by: * * Loading the instruction register with the SWI instruction Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted.
Data Sheet 116 Central Processor Unit (CPU) MC68HC908GZ8 MOTOROLA
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Freescale Semiconductor, Inc.
Central Processor Unit (CPU) Instruction Set Summary
10.7 Instruction Set Summary
Table 10-1 provides a summary of the M68HC08 instruction set. Table 10-1. Instruction Set Summary (Sheet 1 of 7)
Opcode Source Form
ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADC opr,SP ADC opr,SP ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X ADD opr,SP ADD opr,SP AIS #opr AIX #opr AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X AND opr,SP AND opr,SP ASL opr ASLA ASLX ASL opr,X ASL ,X ASL opr,SP ASR opr ASRA ASRX ASR opr,X ASR opr,X ASR opr,SP BCC rel
Operation
Description
VH I NZC
Add with Carry
A (A) + (M) + (C)
-
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IMM DIR EXT IX2 IX1 IX SP1 SP2 IMM DIR EXT IX2 IX1 IX SP1 SP2
A9 B9 C9 D9 E9 F9 9EE9 9ED9 AB BB CB DB EB FB 9EEB 9EDB A7 AF A4 B4 C4 D4 E4 F4 9EE4 9ED4
ii dd hh ll ee ff ff ff ee ff ii dd hh ll ee ff ff ff ee ff ii ii ii dd hh ll ee ff ff ff ee ff
Add without Carry
A (A) + (M)
-
Add Immediate Value (Signed) to SP Add Immediate Value (Signed) to H:X
SP (SP) + (16 M) H:X (H:X) + (16 M)
- - - - - - IMM - - - - - - IMM IMM DIR EXT IX2 - IX1 IX SP1 SP2 DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1
Logical AND
A (A) & (M)
0--
Arithmetic Shift Left (Same as LSL)
C b7 b0
0
--
38 dd 48 58 68 ff 78 9E68 ff 37 dd 47 57 67 ff 77 9E67 ff 24 11 13 15 17 19 1B 1D 1F 25 27 rr dd dd dd dd dd dd dd dd rr rr
Arithmetic Shift Right
b7 b0
C
--
Branch if Carry Bit Clear
PC (PC) + 2 + rel ? (C) = 0
- - - - - - REL DIR (b0) DIR (b1) DIR (b2) - - - - - - DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) - - - - - - REL - - - - - - REL
BCLR n, opr
Clear Bit n in M
Mn 0
BCS rel BEQ rel
Branch if Carry Bit Set (Same as BLO) Branch if Equal
PC (PC) + 2 + rel ? (C) = 1 PC (PC) + 2 + rel ? (Z) = 1
MC68HC908GZ8 MOTOROLA Central Processor Unit (CPU)
Data Sheet 117
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Cycles
2 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5 2 2 2 3 4 4 3 2 4 5 4 1 1 4 3 5 4 1 1 4 3 5 3 4 4 4 4 4 4 4 4 3 3
Effect on CCR
Operand
Address Mode
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Table 10-1. Instruction Set Summary (Sheet 2 of 7)
Opcode Source Form
BGE opr BGT opr BHCC rel BHCS rel
Operation
Branch if Greater Than or Equal To (Signed Operands) Branch if Greater Than (Signed Operands) Branch if Half Carry Bit Clear Branch if Half Carry Bit Set Branch if Higher Branch if Higher or Same (Same as BCC) Branch if IRQ Pin High Branch if IRQ Pin Low
Description
PC (PC) + 2 + rel ? (N V) = 0
VH I NZC
- - - - - - REL
90 92 28 29 22 24 2F 2E A5 B5 C5 D5 E5 F5 9EE5 9ED5 93 25 23 91 2C 2B 2D 26 2A 20 01 03 05 07 09 0B 0D 0F 21
rr rr rr rr rr rr rr rr ii dd hh ll ee ff ff ff ee ff rr rr rr rr rr rr rr rr rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr
PC (PC) + 2 + rel ? (Z) | (N V) = 0 - - - - - - REL PC (PC) + 2 + rel ? (H) = 0 PC (PC) + 2 + rel ? (H) = 1 PC (PC) + 2 + rel ? (C) | (Z) = 0 PC (PC) + 2 + rel ? (C) = 0 PC (PC) + 2 + rel ? IRQ = 1 PC (PC) + 2 + rel ? IRQ = 0 - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL IMM DIR EXT - IX2 IX1 IX SP1 SP2
3 3 3 3 3 2 3 4 4 3 2 4 5 3 3 3 3 3 3 3 3 3 3 5 5 5 5 5 5 5 5 3
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BHI rel BHS rel BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP BLE opr BLO rel BLS rel BLT opr BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel
Bit Test
(A) & (M)
0--
Branch if Less Than or Equal To (Signed Operands) Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Less Than (Signed Operands) Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always
PC (PC) + 2 + rel ? (Z) | (N V) = 1 - - - - - - REL PC (PC) + 2 + rel ? (C) = 1 PC (PC) + 2 + rel ? (C) | (Z) = 1 PC (PC) + 2 + rel ? (N V) =1 PC (PC) + 2 + rel ? (I) = 0 PC (PC) + 2 + rel ? (N) = 1 PC (PC) + 2 + rel ? (I) = 1 PC (PC) + 2 + rel ? (Z) = 0 PC (PC) + 2 + rel ? (N) = 0 PC (PC) + 2 + rel - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)
BRCLR n,opr,rel Branch if Bit n in M Clear
PC (PC) + 3 + rel ? (Mn) = 0
-----
BRN rel
Branch Never
PC (PC) + 2
- - - - - - REL
Data Sheet 118 Central Processor Unit (CPU)
MC68HC908GZ8 MOTOROLA
For More Information On This Product, Go to: www.freescale.com
Cycles
3 3 3
Effect on CCR
Operand
Address Mode
Freescale Semiconductor, Inc.
Central Processor Unit (CPU) Instruction Set Summary
Table 10-1. Instruction Set Summary (Sheet 3 of 7)
Opcode Source Form Operation Description Cycles
5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 5 4 4 5 4 6 1 2 3 1 1 1 3 2 4 2 3 4 4 3 2 4 5 4 1 1 4 3 5 3 4
Effect on CCR VH I NZC
BRSET n,opr,rel Branch if Bit n in M Set
PC (PC) + 3 + rel ? (Mn) = 1
-----
DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)
00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E
dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd dd dd dd dd dd dd dd
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BSET n,opr
Set Bit n in M
Mn 1
DIR (b0) DIR (b1) DIR (b2) DIR (b3) - - - - - - DIR (b4) DIR (b5) DIR (b6) DIR (b7)
BSR rel
Branch to Subroutine
PC (PC) + 2; push (PCL) SP (SP) - 1; push (PCH) SP (SP) - 1 PC (PC) + rel PC (PC) + 3 + rel ? (A) - (M) = $00 PC (PC) + 3 + rel ? (A) - (M) = $00 PC (PC) + 3 + rel ? (X) - (M) = $00 PC (PC) + 3 + rel ? (A) - (M) = $00 PC (PC) + 2 + rel ? (A) - (M) = $00 PC (PC) + 4 + rel ? (A) - (M) = $00 C0 I0 M $00 A $00 X $00 H $00 M $00 M $00 M $00
- - - - - - REL
AD
rr
CBEQ opr,rel CBEQA #opr,rel CBEQX #opr,rel Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel CLC CLI CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP COM opr COMA COMX COM opr,X COM ,X COM opr,SP CPHX #opr CPHX opr Clear Carry Bit Clear Interrupt Mask
DIR IMM - - - - - - IMM IX1+ IX+ SP1 - - - - - 0 INH - - 0 - - - INH DIR INH INH 0 - - 0 1 - INH IX1 IX SP1 IMM DIR EXT IX2 IX1 IX SP1 SP2 DIR INH INH 1 IX1 IX SP1 IMM DIR
31 41 51 61 71 9E61 98 9A
dd rr ii rr ii rr ff rr rr ff rr
Clear
3F dd 4F 5F 8C 6F ff 7F 9E6F ff A1 B1 C1 D1 E1 F1 9EE1 9ED1 ii dd hh ll ee ff ff ff ee ff
Compare A with M
(A) - (M)
--
Complement (One's Complement)
M (M) = $FF - (M) A (A) = $FF - (M) X (X) = $FF - (M) M (M) = $FF - (M) M (M) = $FF - (M) M (M) = $FF - (M) (H:X) - (M:M + 1)
0--
33 dd 43 53 63 ff 73 9E63 ff 65 75 ii ii+1 dd
Compare H:X with M
--
MC68HC908GZ8 MOTOROLA Central Processor Unit (CPU)
Data Sheet 119
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Operand
Address Mode
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Table 10-1. Instruction Set Summary (Sheet 4 of 7)
Opcode Source Form
CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP DAA
Operation
Description
VH I NZC
Compare X with M
(X) - (M)
--
IMM DIR EXT IX2 IX1 IX SP1 SP2 INH
A3 B3 C3 D3 E3 F3 9EE3 9ED3 72 3B 4B 5B 6B 7B 9E6B
ii dd hh ll ee ff ff ff ee ff
Decimal Adjust A
(A)10
U--
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DBNZ opr,rel DBNZA rel DBNZX rel Decrement and Branch if Not Zero DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP DIV EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EOR opr,SP EOR opr,SP INC opr INCA INCX INC opr,X INC ,X INC opr,SP JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDA opr,SP LDA opr,SP
A (A) - 1 or M (M) - 1 or X (X) - 1 PC (PC) + 3 + rel ? (result) 0 DIR PC (PC) + 2 + rel ? (result) 0 INH PC (PC) + 2 + rel ? (result) 0 - - - - - - INH PC (PC) + 3 + rel ? (result) 0 IX1 PC (PC) + 2 + rel ? (result) 0 IX PC (PC) + 4 + rel ? (result) 0 SP1 M (M) - 1 A (A) - 1 X (X) - 1 M (M) - 1 M (M) - 1 M (M) - 1 A (H:A)/(X) H Remainder DIR INH - INH IX1 IX SP1 INH IMM DIR EXT IX2 - IX1 IX SP1 SP2 DIR INH INH - IX1 IX SP1
dd rr rr rr ff rr rr ff rr
Decrement
--
3A dd 4A 5A 6A ff 7A 9E6A ff 52 A8 B8 C8 D8 E8 F8 9EE8 9ED8 ii dd hh ll ee ff ff ff ee ff
Divide
----
Exclusive OR M with A
A (A M)
0--
Increment
M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1 M (M) + 1
--
3C dd 4C 5C 6C ff 7C 9E6C ff BC CC DC EC FC BD CD DD ED FD A6 B6 C6 D6 E6 F6 9EE6 9ED6 dd hh ll ee ff ff dd hh ll ee ff ff ii dd hh ll ee ff ff ff ee ff
Jump
PC Jump Address
DIR EXT - - - - - - IX2 IX1 IX DIR EXT - - - - - - IX2 IX1 IX IMM DIR EXT - IX2 IX1 IX SP1 SP2
Jump to Subroutine
PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) - 1 Push (PCH); SP (SP) - 1 PC Unconditional Address
Load A from M
A (M)
0--
Data Sheet 120 Central Processor Unit (CPU)
MC68HC908GZ8 MOTOROLA
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Cycles
2 3 4 4 3 2 4 5 2 5 3 3 5 4 6 4 1 1 4 3 5 7 2 3 4 4 3 2 4 5 4 1 1 4 3 5 2 3 4 3 2 4 5 6 5 4 2 3 4 4 3 2 4 5
Effect on CCR
Operand
Address Mode
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Central Processor Unit (CPU) Instruction Set Summary
Table 10-1. Instruction Set Summary (Sheet 5 of 7)
Opcode Source Form
LDHX #opr LDHX opr LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LDX opr,SP LDX opr,SP LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP MOV opr,opr MOV opr,X+ MOV #opr,opr MOV X+,opr MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NEG opr,SP NOP NSA ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ORA opr,SP ORA opr,SP PSHA PSHH PSHX PULA PULH PULX
Operation
Description
H:X (M:M + 1)
VH I NZC
Load H:X from M 0--
IMM - DIR IMM DIR EXT IX2 - IX1 IX SP1 SP2 DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1 DD DIX+ IMD IX+D
45 55 AE BE CE DE EE FE 9EEE 9EDE
ii jj dd ii dd hh ll ee ff ff ff ee ff
Load X from M
X (M)
0--
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Logical Shift Left (Same as ASL)
C b7 b0
0
--
38 dd 48 58 68 ff 78 9E68 ff 34 dd 44 54 64 ff 74 9E64 ff 4E 5E 6E 7E 42 30 dd 40 50 60 ff 70 9E60 ff 9D 62 AA BA CA DA EA FA 9EEA 9EDA 87 8B 89 86 8A 88 ii dd hh ll ee ff ff ff ee ff dd dd dd ii dd dd
Logical Shift Right
0 b7 b0
C
--0
Move
(M)Destination (M)Source H:X (H:X) + 1 (IX+D, DIX+) X:A (X) x (A) M -(M) = $00 - (M) A -(A) = $00 - (A) X -(X) = $00 - (X) M -(M) = $00 - (M) M -(M) = $00 - (M) None A (A[3:0]:A[7:4])
0--
-
Unsigned multiply
- 0 - - - 0 INH DIR INH INH IX1 IX SP1
Negate (Two's Complement)
--
No Operation Nibble Swap A
- - - - - - INH - - - - - - INH IMM DIR EXT IX2 - IX1 IX SP1 SP2
Inclusive OR A and M
A (A) | (M)
0--
Push A onto Stack Push H onto Stack Push X onto Stack Pull A from Stack Pull H from Stack Pull X from Stack
Push (A); SP (SP) - 1 Push (H); SP (SP) - 1 Push (X); SP (SP) - 1 SP (SP + 1); Pull (A) SP (SP + 1); Pull (H) SP (SP + 1); Pull (X)
- - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH
MC68HC908GZ8 MOTOROLA Central Processor Unit (CPU)
Data Sheet 121
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Cycles
3 4 2 3 4 4 3 2 4 5 4 1 1 4 3 5 4 1 1 4 3 5 5 4 4 4 5 4 1 1 4 3 5 1 3 2 3 4 4 3 2 4 5 2 2 2 2 2 2
Effect on CCR
Operand
Address Mode
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Table 10-1. Instruction Set Summary (Sheet 6 of 7)
Opcode Source Form
ROL opr ROLA ROLX ROL opr,X ROL ,X ROL opr,SP ROR opr RORA RORX ROR opr,X ROR ,X ROR opr,SP RSP
Operation
Description
VH I NZC
Rotate Left through Carry
C b7 b0
--
DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1
39 dd 49 59 69 ff 79 9E69 ff 36 dd 46 56 66 ff 76 9E66 ff 9C
Rotate Right through Carry
b7 b0
C
--
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Reset Stack Pointer
SP $FF SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) SP SP + 1; Pull (PCH) SP SP + 1; Pull (PCL)
- - - - - - INH
RTI
Return from Interrupt
INH
80
RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SBC opr,SP SBC opr,SP SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STA opr,SP STA opr,SP STHX opr STOP STX opr STX opr STX opr,X STX opr,X STX ,X STX opr,SP STX opr,SP SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X SUB opr,SP SUB opr,SP
Return from Subroutine
- - - - - - INH IMM DIR EXT IX2 IX1 IX SP1 SP2
81 A2 B2 C2 D2 E2 F2 9EE2 9ED2 99 9B B7 C7 D7 E7 F7 9EE7 9ED7 35 8E BF CF DF EF FF 9EEF 9EDF A0 B0 C0 D0 E0 F0 9EE0 9ED0 dd hh ll ee ff ff ff ee ff ii dd hh ll ee ff ff ff ee ff dd hh ll ee ff ff ff ee ff dd ii dd hh ll ee ff ff ff ee ff
Subtract with Carry
A (A) - (M) - (C)
--
Set Carry Bit Set Interrupt Mask
C1 I1
- - - - - 1 INH - - 1 - - - INH DIR EXT IX2 - IX1 IX SP1 SP2 - DIR
Store A in M
M (A)
0--
Store H:X in M Enable IRQ Pin; Stop Oscillator
(M:M + 1) (H:X) I 0; Stop Oscillator
0--
- - 0 - - - INH DIR EXT IX2 - IX1 IX SP1 SP2 IMM DIR EXT IX2 IX1 IX SP1 SP2
Store X in M
M (X)
0--
Subtract
A (A) - (M)
--
Data Sheet 122 Central Processor Unit (CPU)
MC68HC908GZ8 MOTOROLA
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Cycles
4 1 1 4 3 5 4 1 1 4 3 5 1 7 4 2 3 4 4 3 2 4 5 1 2 3 4 4 3 2 4 5 4 1 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5
Effect on CCR
Operand
Address Mode
Freescale Semiconductor, Inc.
Central Processor Unit (CPU) Opcode Map
Table 10-1. Instruction Set Summary (Sheet 7 of 7)
Opcode Source Form Operation Description
PC (PC) + 1; Push (PCL) SP (SP) - 1; Push (PCH) SP (SP) - 1; Push (X) SP (SP) - 1; Push (A) SP (SP) - 1; Push (CCR) SP (SP) - 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte CCR (A) X (A) A (CCR)
VH I NZC
SWI
Software Interrupt
- - 1 - - - INH
83
TAP
Transfer A to CCR Transfer A to X Transfer CCR to A
INH - - - - - - INH - - - - - - INH DIR INH - INH IX1 IX SP1
84 97 85 3D dd 4D 5D 6D ff 7D 9E6D ff 95 9F 94
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TAX TPA TST opr TSTA TSTX TST opr,X TST ,X TST opr,SP TSX TXA TXS A C CCR dd dd rr DD DIR DIX+ ee ff EXT ff H H hh ll I ii IMD IMM INH IX IX+ IX+D IX1 IX1+ IX2 M N
Test for Negative or Zero
(A) - $00 or (X) - $00 or (M) - $00
0--
Transfer SP to H:X Transfer X to A Transfer H:X to SP
H:X (SP) + 1 A (X) (SP) (H:X) - 1 n opr PC PCH PCL REL rel rr SP1 SP2 SP U V X Z & |
- - - - - - INH - - - - - - INH - - - - - - INH
Accumulator Carry/borrow bit Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct to direct addressing mode Direct addressing mode Direct to indexed with post increment addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry bit Index register high byte High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate source to direct destination addressing mode Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, no offset, post increment addressing mode Indexed with post increment to direct addressing mode Indexed, 8-bit offset addressing mode Indexed, 8-bit offset, post increment addressing mode Indexed, 16-bit offset addressing mode Memory location Negative bit
() -( ) # ? : --
Any bit Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer, 8-bit offset addressing mode Stack pointer 16-bit offset addressing mode Stack pointer Undefined Overflow bit Index register low byte Zero bit Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two's complement) Immediate value Sign extend Loaded with If Concatenated with Set or cleared Not affected
10.8 Opcode Map
See Table 10-2.
MC68HC908GZ8 MOTOROLA Central Processor Unit (CPU)
Data Sheet 123
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Cycles
9 2 1 1 3 1 1 3 2 4 2 1 2
Effect on CCR
Operand
Address Mode
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Table 10-2. Opcode Map
DIR 3 4 5 6 9E6 7 8 9 A B C D 9ED E 9EE F INH Read-Modify-Write INH IX1 SP1 IX IMM DIR EXT IX1 SP1 IX Control INH INH Register/Memory IX2 SP2 2
Central Processor Unit (CPU)
124
2 SUB 2 IMM 2 CMP 2 IMM 2 SBC 2 IMM 2 CPX 2 IMM 2 AND 2 IMM 2 BIT 2 IMM 2 LDA 2 IMM 2 AIS 2 IMM 2 EOR 2 IMM 2 ADC 2 IMM 2 ORA 2 IMM 2 ADD 2 IMM 5 SUB 4 SP2 5 CMP 4 SP2 5 SBC 4 SP2 5 CPX 4 SP2 5 AND 4 SP2 5 BIT 4 SP2 5 LDA 4 SP2 5 STA 4 SP2 5 EOR 4 SP2 5 ADC 4 SP2 5 ORA 4 SP2 5 ADD 4 SP2 4 SUB 3 SP1 4 CMP 3 SP1 4 SBC 3 SP1 4 CPX 3 SP1 4 AND 3 SP1 4 BIT 3 SP1 4 LDA 3 SP1 4 STA 3 SP1 4 EOR 3 SP1 4 ADC 3 SP1 4 ORA 3 SP1 4 ADD 3 SP1 4 1 NEG NEGA 2 DIR 1 INH 5 4 CBEQ CBEQA 3 DIR 3 IMM 5 MUL 1 INH 4 1 COM COMA 2 DIR 1 INH 4 1 LSR LSRA 2 DIR 1 INH 4 3 STHX LDHX 2 DIR 3 IMM 4 1 ROR RORA 2 DIR 1 INH 4 1 ASR ASRA 2 DIR 1 INH 4 1 LSL LSLA 2 DIR 1 INH 4 1 ROL ROLA 2 DIR 1 INH 4 1 DEC DECA 2 DIR 1 INH 5 3 DBNZ DBNZA 3 DIR 2 INH 4 1 INC INCA 2 DIR 1 INH 3 1 TST TSTA 2 DIR 1 INH 5 MOV 3 DD 3 1 CLR CLRA 2 DIR 1 INH
MSB LSB
Data Sheet
Bit Manipulation DIR DIR
Branch REL
MSB
0
1
LSB
0
1
2
3
4
5
6
7
8
9
Central Processor Unit (CPU)
0 Low Byte of Opcode in Hexadecimal 0 SP1 Stack Pointer, 8-Bit Offset SP2 Stack Pointer, 16-Bit Offset IX+ Indexed, No Offset with Post Increment IX1+ Indexed, 1-Byte Offset with Post Increment
A
B
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C
D
E
F
5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR
4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR
3 BRA 2 REL 3 BRN 2 REL 3 BHI 2 REL 3 BLS 2 REL 3 BCC 2 REL 3 BCS 2 REL 3 BNE 2 REL 3 BEQ 2 REL 3 BHCC 2 REL 3 BHCS 2 REL 3 BPL 2 REL 3 BMI 2 REL 3 BMC 2 REL 3 BMS 2 REL 3 BIL 2 REL 3 BIH 2 REL
1 NEGX 1 INH 4 CBEQX 3 IMM 7 DIV 1 INH 1 COMX 1 INH 1 LSRX 1 INH 4 LDHX 2 DIR 1 RORX 1 INH 1 ASRX 1 INH 1 LSLX 1 INH 1 ROLX 1 INH 1 DECX 1 INH 3 DBNZX 2 INH 1 INCX 1 INH 1 TSTX 1 INH 4 MOV 2 DIX+ 1 CLRX 1 INH
4 NEG 2 IX1 5 CBEQ 3 IX1+ 3 NSA 1 INH 4 COM 2 IX1 4 LSR 2 IX1 3 CPHX 3 IMM 4 ROR 2 IX1 4 ASR 2 IX1 4 LSL 2 IX1 4 ROL 2 IX1 4 DEC 2 IX1 5 DBNZ 3 IX1 4 INC 2 IX1 3 TST 2 IX1 4 MOV 3 IMD 3 CLR 2 IX1
5 3 NEG NEG 3 SP1 1 IX 6 4 CBEQ CBEQ 4 SP1 2 IX+ 2 DAA 1 INH 5 3 COM COM 3 SP1 1 IX 5 3 LSR LSR 3 SP1 1 IX 4 CPHX 2 DIR 5 3 ROR ROR 3 SP1 1 IX 5 3 ASR ASR 3 SP1 1 IX 5 3 LSL LSL 3 SP1 1 IX 5 3 ROL ROL 3 SP1 1 IX 5 3 DEC DEC 3 SP1 1 IX 6 4 DBNZ DBNZ 4 SP1 2 IX 5 3 INC INC 3 SP1 1 IX 4 2 TST TST 3 SP1 1 IX 4 MOV 2 IX+D 4 2 CLR CLR 3 SP1 1 IX
7 3 RTI BGE 1 INH 2 REL 4 3 RTS BLT 1 INH 2 REL 3 BGT 2 REL 9 3 SWI BLE 1 INH 2 REL 2 2 TAP TXS 1 INH 1 INH 1 2 TPA TSX 1 INH 1 INH 2 PULA 1 INH 2 1 PSHA TAX 1 INH 1 INH 2 1 PULX CLC 1 INH 1 INH 2 1 PSHX SEC 1 INH 1 INH 2 2 PULH CLI 1 INH 1 INH 2 2 PSHH SEI 1 INH 1 INH 1 1 CLRH RSP 1 INH 1 INH 1 NOP 1 INH 1 STOP * 1 INH 1 1 WAIT TXA 1 INH 1 INH
3 SUB 2 DIR 3 CMP 2 DIR 3 SBC 2 DIR 3 CPX 2 DIR 3 AND 2 DIR 3 BIT 2 DIR 3 LDA 2 DIR 3 STA 2 DIR 3 EOR 2 DIR 3 ADC 2 DIR 3 ORA 2 DIR 3 ADD 2 DIR 2 JMP 2 DIR 4 4 BSR JSR 2 REL 2 DIR 2 3 LDX LDX 2 IMM 2 DIR 2 3 AIX STX 2 IMM 2 DIR
4 SUB 3 EXT 4 CMP 3 EXT 4 SBC 3 EXT 4 CPX 3 EXT 4 AND 3 EXT 4 BIT 3 EXT 4 LDA 3 EXT 4 STA 3 EXT 4 EOR 3 EXT 4 ADC 3 EXT 4 ORA 3 EXT 4 ADD 3 EXT 3 JMP 3 EXT 5 JSR 3 EXT 4 LDX 3 EXT 4 STX 3 EXT
4 SUB 3 IX2 4 CMP 3 IX2 4 SBC 3 IX2 4 CPX 3 IX2 4 AND 3 IX2 4 BIT 3 IX2 4 LDA 3 IX2 4 STA 3 IX2 4 EOR 3 IX2 4 ADC 3 IX2 4 ORA 3 IX2 4 ADD 3 IX2 4 JMP 3 IX2 6 JSR 3 IX2 4 LDX 3 IX2 4 STX 3 IX2
3 SUB 2 IX1 3 CMP 2 IX1 3 SBC 2 IX1 3 CPX 2 IX1 3 AND 2 IX1 3 BIT 2 IX1 3 LDA 2 IX1 3 STA 2 IX1 3 EOR 2 IX1 3 ADC 2 IX1 3 ORA 2 IX1 3 ADD 2 IX1 3 JMP 2 IX1 5 JSR 2 IX1 5 3 LDX LDX 4 SP2 2 IX1 5 3 STX STX 4 SP2 2 IX1
2 SUB 1 IX 2 CMP 1 IX 2 SBC 1 IX 2 CPX 1 IX 2 AND 1 IX 2 BIT 1 IX 2 LDA 1 IX 2 STA 1 IX 2 EOR 1 IX 2 ADC 1 IX 2 ORA 1 IX 2 ADD 1 IX 2 JMP 1 IX 4 JSR 1 IX 4 2 LDX LDX 3 SP1 1 IX 4 2 STX STX 3 SP1 1 IX
MC68HC908GZ8
Inherent REL Relative Immediate IX Indexed, No Offset Direct IX1 Indexed, 8-Bit Offset Extended IX2 Indexed, 16-Bit Offset Direct-Direct IMD Immediate-Direct Indexed-Direct DIX+ Direct-Indexed *Pre-byte for stack pointer indexed instructions
INH IMM DIR EXT DD IX+D
High Byte of Opcode in Hexadecimal 5 Cycles BRSET0 Opcode Mnemonic 3 DIR Number of Bytes / Addressing Mode
MOTOROLA
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Data Sheet -- MC68HC908GZ8
Section 11. FLASH Memory (FLASH)
11.1 Introduction
This section describes the operation of the embedded FLASH memory. This memory can be read, programmed, and erased from a single external supply. The program, erase, and read operations are enabled through the use of an internal charge pump. It is recommended that the user utilize the FLASH programming routines provided in the on-chip ROM, which are described more fully in a separate Motorola application note.
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11.2 Functional Description
The FLASH memory is an array of 7936 bytes with an additional 44 bytes of user vectors and one byte of block protection. An erased bit reads as logic 1 and a programmed bit reads as a logic 0. Memory in the FLASH array is organized into two rows per page basis. For the 16-K word by 8-bit embedded FLASH memory, the page size is 64 bytes per page and the row size is 32 bytes per row. Hence the minimum erase page size is 64 bytes and the minimum program row size is 32 bytes. Program and erase operation operations are facilitated through control bits in FLASH control register (FLCR). Details for these operations appear later in this section. The address ranges for the user memory and vectors are: * * * * $E000-$FDFF; user memory $FE08; FLASH control register $FF7E; FLASH block protect register $FFD4-$FFFF; these locations are reserved for user-defined interrupt and reset vectors
Programming tools are available from Motorola. Contact your local Motorola representative for more information. NOTE: A security feature prevents viewing of the FLASH contents.(1)
1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908GZ8 MOTOROLA FLASH Memory (FLASH) Data Sheet 125
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FLASH Memory (FLASH)
11.3 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program and erase operations.
Address: Read: Write: Reset: 0 0 = Unimplemented 0 0 $FE08 Bit 7 0 6 0 5 0 4 0 3 HVEN 0 2 MASS 0 1 ERASE 0 Bit 0 PGM 0
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Figure 11-1. FLASH Control Register (FLCR) HVEN -- High-Voltage Enable Bit This read/write bit enables the charge pump to drive high voltages for program and erase operations in the array. HVEN can only be set if either PGM = 1 or ERASE = 1 and the proper sequence for program or erase is followed. 1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off MASS -- Mass Erase Control Bit Setting this read/write bit configures the 16-Kbyte FLASH array for mass erase operation. 1 = MASS erase operation selected 0 = PAGE erase operation selected ERASE -- Erase Control Bit This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = Erase operation selected 0 = Erase operation unselected PGM -- Program Control Bit This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = Program operation selected 0 = Program operation unselected
Data Sheet 126 FLASH Memory (FLASH)
MC68HC908GZ8 MOTOROLA
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FLASH Memory (FLASH) FLASH Page Erase Operation
11.4 FLASH Page Erase Operation
Use this step-by-step procedure to erase a page (64 bytes) of FLASH memory to read as logic 1. A page consists of 64 consecutive bytes starting from addresses $XX00, $XX40, $XX80, or $XXC0. The 44-byte user interrupt vectors area also forms a page. Any FLASH memory page can be erased alone. 1. Set the ERASE bit, and clear the MASS bit in the FLASH control register. 2. Read the FLASH block protect register. 3. Write any data to any FLASH address within the page address range desired. 4. Wait for a time, tNVS (minimum 10 s) 5. Set the HVEN bit. 6. Wait for a time, tErase (minimum 1 ms or 4 ms) 7. Clear the ERASE bit. 8. Wait for a time, tNVH (minimum 5 s) 9. Clear the HVEN bit. 10. After a time, tRCV (typical 1 s), the memory can be accessed again in read mode. NOTE: Programming and erasing of FLASH locations cannot be performed by code being executed from FLASH memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. It is highly recommended that interrupts be disabled during program/ erase operations. In applications that need more than 1000 program/erase cycles, use the 4-ms page erase specification to get improved long-term reliability. Any application can use this 4-ms page erase specification. However, in applications where a FLASH location will be erased and reprogrammed less than 1000 times, and speed is important, use the 1-ms page erase specification to get a lower minimum erase time.
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NOTE: NOTE:
MC68HC908GZ8 MOTOROLA FLASH Memory (FLASH)
Data Sheet 127
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FLASH Memory (FLASH)
11.5 FLASH Mass Erase Operation
Use this step-by-step procedure to erase entire FLASH memory to read as logic 1: 1. Set both the ERASE bit, and the MASS bit in the FLASH control register. 2. Read from the FLASH block protect register. 3. Write any data to any FLASH address(1) within the FLASH memory address range. 4. Wait for a time, tNVS (minimum 10 s) 5. Set the HVEN bit. 6. Wait for a time, tMErase (minimum 4 ms) 7. Clear the ERASE and MASS bits. 8. Wait for a time, tNVHL (minimum 100 s) 9. Clear the HVEN bit. 10. After a time, tRCV (minimum 1 s), the memory can be accessed again in read mode. NOTE: NOTE: Mass erase is disabled whenever any block is protected (FLBPR does not equal $FF). Programming and erasing of FLASH locations cannot be performed by code being executed from FLASH memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps.
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11.6 FLASH Program/Read Operation
Programming of the FLASH memory is done on a row basis. A row consists of 32 consecutive bytes starting from addresses $XX00, $XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0, and $XXE0. During the programming cycle, make sure that all addresses being written to fit within one of the ranges specified above. Attempts to program addresses in different row ranges in one programming cycle will fail. Use this step-by-step procedure to program a row of FLASH memory (Figure 11-2 is a flowchart representation). NOTE: Only bytes which are currently $FF may be programmed. 1. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming. 2. Read from the FLASH block protect register. 3. Write any data to any FLASH address within the row address range desired. 4. Wait for a time, tNVS (minimum 10 s).
1. When in monitor mode, with security sequence failed (see 15.4 Security), write to the FLASH block protect register instead of any FLASH address. Data Sheet 128 FLASH Memory (FLASH) MC68HC908GZ8 MOTOROLA
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FLASH Memory (FLASH) FLASH Program/Read Operation
5. 6. 7. 8. 9. 10. 11. 12. 13.
Set the HVEN bit. Wait for a time, tPGS (minimum 5 s). Write data to the FLASH address to be programmed. Wait for a time, tPROG (30-40 s). Repeat step 7 and 8 until all the bytes within the row are programmed. Clear the PGM bit.(1) Wait for a time, tNVH (minimum 5 s). Clear the HVEN bit. After time, tRCV (minimum 1 s), the memory can be accessed in read mode again.
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This program sequence is repeated throughout the memory until all data is programmed. NOTE: NOTE: Programming and erasing of FLASH locations can not be performed by code being executed from the same FLASH array. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. Care must be taken within the FLASH array memory space such as the COP control register (COPCTL) at $FFFF. It is highly recommended that interrupts be disabled during program/ erase operations. Do not exceed tPROG maximum or tHV maximum. tHV is defined as the cumulative high voltage programming time to the same row before next erase. tHV must satisfy this condition: tNVS + tNVH + tPGS + (tPROG x 32) tHV maximum Refer to 24.15 Memory Characteristics. NOTE: The time between programming the FLASH address change (step 7 to step 7), or the time between the last FLASH programmed to clearing the PGM bit (step 7 to step 10) must not exceed the maximum programming time, tPROG maximum. Be cautious when programming the FLASH array to ensure that non-FLASH locations are not used as the address that is written to when selecting either the desired row address range in step 3 of the algorithm or the byte to be programmed in step 7 of the algorithm. This applies particularly to $FFD4-$FFDF.
NOTE: NOTE:
CAUTION:
MC68HC908GZ8 MOTOROLA FLASH Memory (FLASH)
Data Sheet 129
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FLASH Memory (FLASH)
Algorithm for programming a row (32 bytes) of FLASH memory
1
SET PGM BIT
2
READ THE FLASH BLOCK PROTECT REGISTER
3
WRITE ANY DATA TO ANY FLASH ADDRESS WITHIN THE ROW ADDRESS RANGE DESIRED
4
WAIT FOR A TIME, tNVS
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5
SET HVEN BIT
6
WAIT FOR A TIME, tPGS
7
WRITE DATA TO THE FLASH ADDRESS TO BE PROGRAMMED
8
WAIT FOR A TIME, tPROG
COMPLETED PROGRAMMING THIS ROW? N 10
Y
CLEAR PGM BIT
11
WAIT FOR A TIME, tNVH
Note: The time between each FLASH address change (step 7 to step 7), or the time between the last FLASH address programmed to clearing PGM bit (step 7 to step 10) must not exceed the maximum programming time, tPROG max. This row program algorithm assumes the row/s to be programmed are initially erased.
12 CLEAR HVEN BIT
13
WAIT FOR A TIME, tRCV
END OF PROGRAMMING
Figure 11-2. FLASH Programming Flowchart
Data Sheet 130 FLASH Memory (FLASH)
MC68HC908GZ8 MOTOROLA
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FLASH Memory (FLASH) FLASH Block Protection
11.7 FLASH Block Protection
Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made for protecting a block of memory from unintentional erase or program operations due to system malfunction. This protection is done by using of a FLASH block protect register (FLBPR). The FLBPR determines the range of the FLASH memory which is to be protected. The range of the protected area starts from a location defined by FLBPR and ends at the bottom of the FLASH memory ($FFFF). When the memory is protected, the HVEN bit cannot be set in either ERASE or PROGRAM operations. NOTE: In performing a program or erase operation, the FLASH block protect register must be read after setting the PGM or ERASE bit and before asserting the HVEN bit When the FLBPR is program with all 0's, the entire memory is protected from being programmed and erased. When all the bits are erased (all 1's), the entire memory is accessible for program and erase. When bits within the FLBPR are programmed, they lock a block of memory, address ranges as shown in 11.7.1 FLASH Block Protect Register. Once the FLBPR is programmed with a value other than $FF, any erase or program of the FLBPR or the protected block of FLASH memory is prohibited. The presence of a VTST on the IRQ pin will bypass the block protection so that all of the memory included in the block protect register is open for program and erase operations. NOTE: The FLASH block protect register is not protected with special hardware or software. Therefore, if this page is not protected by FLBPR the register is erased by either a page or mass erase operation.
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11.7.1 FLASH Block Protect Register The FLASH block protect register (FLBPR) is implemented as a byte within the FLASH memory, and therefore can only be written during a programming sequence of the FLASH memory. The value in this register determines the starting location of the protected range within the FLASH memory.
Address: Read: Write: Reset: $FF7E Bit 7 BPR7 U 6 BPR6 U 5 BPR5 U 4 BPR4 U 3 BPR3 U 2 BPR2 U 1 BPR1 U Bit 0 BPR0 U
U = Unaffected by reset. Initial value from factory is 1. Write to this register is by a programming sequence to the FLASH memory.
Figure 11-3. FLASH Block Protect Register (FLBPR)
MC68HC908GZ8 MOTOROLA FLASH Memory (FLASH)
Data Sheet 131
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FLASH Memory (FLASH)
BPR[7:0] -- FLASH Block Protect Bits These eight bits represent bits [13:6] of a 16-bit memory address. Bit-15 and Bit-14 are logic 1s and bits [5:0] are logic 0s. The resultant 16-bit address is used for specifying the start address of the FLASH memory for block protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF. With this mechanism, the protect start address can be $XX00, $XX40, $XX80, and $XXC0 (64 bytes page boundaries) within the FLASH memory.
16-BIT MEMORY ADDRESS START ADDRESS OF FLASH 1 BLOCK PROTECT
1
FLBPR VALUE
0
0
0
0
0
0
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Figure 11-4. FLASH Block Protect Start Address Table 11-1. Examples of Protect Address Ranges
BPR[7:0] $00 $01 (0000 0001) $02 (0000 0010) $03 (0000 0011) $04 (0000 0100) Addresses of Protect Range The entire FLASH memory is protected. $C040 (1100 0000 0100 0000) -- $FFFF $C080 (1100 0000 1000 0000) -- $FFFF $C0C0 (1100 0000 1100 0000) -- $FFFF $C100 (1100 0001 0000 0000) -- $FFFF and so on... $FC (1111 1100) $FD (1111 1101) $FE (1111 1110) $FF $FF00 (1111 1111 0000 0000) -- FFFF $FF40 (1111 1111 0100 0000) -- $FFFF FLBPR and vectors are protected $FF80 (1111 1111 1000 0000) -- FFFF Vectors are protected The entire FLASH memory is not protected.
11.8 Wait Mode
Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly, but there will not be any memory activity since the CPU is inactive. The WAIT instruction should not be executed while performing a program or erase operation on the FLASH, otherwise the operation will discontinue, and the FLASH will be on standby mode.
Data Sheet 132 FLASH Memory (FLASH)
MC68HC908GZ8 MOTOROLA
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FLASH Memory (FLASH) Stop Mode
11.9 Stop Mode
Putting the MCU into stop mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly, but there will not be any memory activity since the CPU is inactive. The STOP instruction should not be executed while performing a program or erase operation on the FLASH, otherwise the operation will discontinue, and the FLASH will be on standby mode NOTE: Standby mode is the power saving mode of the FLASH module in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH is at a minimum.
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MC68HC908GZ8 MOTOROLA
Data Sheet FLASH Memory (FLASH) 133
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FLASH Memory (FLASH)
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Data Sheet 134 FLASH Memory (FLASH)
MC68HC908GZ8 MOTOROLA
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Data Sheet -- MC68HC908GZ8
Section 12. External Interrupt (IRQ)
12.1 Introduction
The IRQ (external interrupt) module provides a maskable interrupt input.
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12.2 Features
Features of the IRQ module include: * * * * * * A dedicated external interrupt pin (IRQ) IRQ interrupt control bits Hysteresis buffer Programmable edge-only or edge and level interrupt sensitivity Automatic interrupt acknowledge Internal pullup resistor
12.3 Functional Description
A logic 0 applied to the external interrupt pin can latch a central processor unit (CPU) interrupt request. Figure 12-1 shows the structure of the IRQ module. Interrupt signals on the IRQ pin are latched into the IRQ latch. An interrupt latch remains set until one of the following actions occurs: * * Vector fetch -- A vector fetch automatically generates an interrupt acknowledge signal that clears the latch that caused the vector fetch. Software clear -- Software can clear an interrupt latch by writing to the appropriate acknowledge bit in the interrupt status and control register (INTSCR). Writing a logic 1 to the ACK bit clears the IRQ latch. Reset -- A reset automatically clears the interrupt latch.
*
The external interrupt pin is falling-edge triggered and is software-configurable to be either falling-edge or falling-edge and low-level triggered. The MODE bit in the INTSCR controls the triggering sensitivity of the IRQ pin. When an interrupt pin is edge-triggered only, the interrupt remains set until a vector fetch, software clear, or reset occurs.
MC68HC908GZ8 MOTOROLA External Interrupt (IRQ)
Data Sheet 135
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External Interrupt (IRQ)
RESET ACK INTERNAL ADDRESS BUS VECTOR FETCH DECODER VDD INTERNAL PULLUP DEVICE IRQ VDD D CLR Q SYNCHRONIZER CK IRQF IRQ INTERRUPT REQUEST TO CPU FOR BIL/BIH INSTRUCTIONS
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IMASK
MODE HIGH VOLTAGE DETECT TO MODE SELECT LOGIC
Figure 12-1. IRQ Module Block Diagram When an interrupt pin is both falling-edge and low-level triggered, the interrupt remains set until both of these events occur: * * Vector fetch or software clear Return of the interrupt pin to logic 1
The vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. As long as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. When set, the IMASK bit in the INTSCR mask all external interrupt requests. A latched interrupt request is not presented to the interrupt priority logic unless the IMASK bit is clear. NOTE: The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt requests.
Bit 7 0 0 6 0 0 = Unimplemented 5 0 0 4 0 0 3 IRQF 0 2 0 ACK 0 1 IMASK 0 Bit 0 MODE 0
Addr.
Register Name
IRQ Status and Control Reg- Read: $001D ister (INTSCR) Write: See page 138. Reset:
Figure 12-2. IRQ I/O Register Summary
Data Sheet 136 External Interrupt (IRQ)
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External Interrupt (IRQ) IRQ Pin
12.4 IRQ Pin
A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE bit is set, the IRQ pin is both falling-edge-sensitive and low-level-sensitive. With MODE set, both of the following actions must occur to clear IRQ: * Vector fetch or software clear -- A vector fetch generates an interrupt acknowledge signal to clear the latch. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACK bit in the interrupt status and control register (INTSCR). The ACK bit is useful in applications that poll the IRQ pin and require software to clear the IRQ latch. Writing to the ACK bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACK does not affect subsequent transitions on the IRQ pin. A falling edge that occurs after writing to the ACK bit another interrupt request. If the IRQ mask bit, IMASK, is clear, the CPU loads the program counter with the vector address at locations $FFFA and $FFFB. Return of the IRQ pin to logic 1 -- As long as the IRQ pin is at logic 0, IRQ remains active.
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*
The vector fetch or software clear and the return of the IRQ pin to logic 1 may occur in any order. The interrupt request remains pending as long as the IRQ pin is at logic 0. A reset will clear the latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. If the MODE bit is clear, the IRQ pin is falling-edge-sensitive only. With MODE clear, a vector fetch or software clear immediately clears the IRQ latch. The IRQF bit in the INTSCR register can be used to check for pending interrupts. The IRQF bit is not affected by the IMASK bit, which makes it useful in applications where polling is preferred. Use the BIH or BIL instruction to read the logic level on the IRQ pin. NOTE: When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine.
12.5 IRQ Module During Break Interrupts
The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear the latch during the break state. See Section 6. Break Module (BRK). To allow software to clear the IRQ latch during a break interrupt, write a logic 1 to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state.
MC68HC908GZ8 MOTOROLA External Interrupt (IRQ)
Data Sheet 137
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External Interrupt (IRQ)
To protect CPU interrupt flags during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), writing to the ACK bit in the IRQ status and control register during the break state has no effect on the IRQ interrupt flags.
12.6 IRQ Status and Control Register
The IRQ status and control register (INTSCR) controls and monitors operation of the IRQ module. The INTSCR: * * * Shows the state of the IRQ flag Clears the IRQ latch Masks IRQ interrupt request Controls triggering sensitivity of the IRQ interrupt pin
$001D Bit 7 Read: Write: Reset: 0 0 = Unimplemented 0 0 0 6 5 4 3 IRQF 2 0 ACK 0 1 IMASK 0 Bit 0 MODE 0
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*
Address:
Figure 12-3. IRQ Status and Control Register (INTSCR) IRQF -- IRQ Flag Bit This read-only status bit is high when the IRQ interrupt is pending. 1 = IRQ interrupt pending 0 = IRQ interrupt not pending ACK -- IRQ Interrupt Request Acknowledge Bit Writing a logic 1 to this write-only bit clears the IRQ latch. ACK always reads as logic 0. Reset clears ACK. IMASK -- IRQ Interrupt Mask Bit Writing a logic 1 to this read/write bit disables IRQ interrupt requests. Reset clears IMASK. 1 = IRQ interrupt requests disabled 0 = IRQ interrupt requests enabled MODE -- IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE. 1 = IRQ interrupt requests on falling edges and low levels 0 = IRQ interrupt requests on falling edges only
Data Sheet 138 External Interrupt (IRQ)
MC68HC908GZ8 MOTOROLA
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Data Sheet -- MC68HC908GZ8
Section 13. Keyboard Interrupt Module (KBI)
13.1 Introduction
The keyboard interrupt module (KBI) provides eight independently maskable external interrupts which are accessible via PTA0-PTA7. When a port pin is enabled for keyboard interrupt function, an internal pullup device is also enabled on the pin.
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13.2 Features
Features include: * * * * * Eight keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt mask Hysteresis buffers Programmable edge-only or edge- and level- interrupt sensitivity Exit from low-power modes I/O (input/output) port bit(s) software configurable with pullup device(s) if configured as input port bit(s)
13.3 Functional Description
Writing to the KBIE7-KBIE0 bits in the keyboard interrupt enable register independently enables or disables each port A pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin also enables its internal pullup device. A logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. A keyboard interrupt is latched when one or more keyboard pins goes low after all were high. The MODEK bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. * If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. To prevent losing an interrupt request on one pin because another pin is still low, software can disable the latter pin while it is low. If the keyboard interrupt is falling edge- and low-level sensitive, an interrupt request is present as long as any keyboard interrupt pin is low and the pin is keyboard interrupt enabled.
*
MC68HC908GZ8 MOTOROLA Keyboard Interrupt Module (KBI)
Data Sheet 139
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Keyboard Interrupt Module (KBI)
INTERNAL BUS
VECTOR FETCH DECODER
ACKK RESET
KBD0 VDD TO PULLUP ENABLE . . KB0IE . KBD7 IMASKK D CLR Q SYNCHRONIZER CK KEYBOARD INTERRUPT REQUEST KEYF
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TO PULLUP ENABLE KB7IE
MODEK
Figure 13-1. Keyboard Module Block Diagram
Addr.
Register Name Keyboard Status Read: and Control Register Write: (INTKBSCR) See page 143. Reset: Keyboard Interrupt Enable Read: Register Write: (INTKBIER) See page 144. Reset:
Bit 7 0
6 0
5 0
4 0
3 KEYF
2 0 ACKK
1 IMASKK 0 KBIE1 0
Bit 0 MODEK 0 KBIE0 0
$001A
0 KBIE7 0
0 KBIE6 0 = Unimplemented
0 KBIE5 0
0 KBIE4 0
0 KBIE3 0
0 KBIE2 0
$001B
Figure 13-2. I/O Register Summary If the MODEK bit is set, the keyboard interrupt pins are both falling edge- and low-level sensitive, and both of the following actions must occur to clear a keyboard interrupt request: * Vector fetch or software clear -- A vector fetch generates an interrupt acknowledge signal to clear the interrupt request. Software may generate the interrupt acknowledge signal by writing a logic 1 to the ACKK bit in the keyboard status and control register (INTKBSCR). The ACKK bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. Writing to the ACKK bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to
MC68HC908GZ8 Keyboard Interrupt Module (KBI) MOTOROLA
Data Sheet 140
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Keyboard Interrupt Module (KBI) Keyboard Initialization
noise. Setting ACKK does not affect subsequent transitions on the keyboard interrupt pins. A falling edge that occurs after writing to the ACKK bit latches another interrupt request. If the keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the program counter with the vector address at locations $FFE0 and $FFE1. * Return of all enabled keyboard interrupt pins to logic 1 -- As long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set.
The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order.
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If the MODEK bit is clear, the keyboard interrupt pin is falling-edge-sensitive only. With MODEK clear, a vector fetch or software clear immediately clears the keyboard interrupt request. Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes it useful in applications where polling is preferred. To determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and read the data register. NOTE: Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. However, the data direction register bit must be a logic 0 for software to read the pin.
13.4 Keyboard Initialization
When a keyboard interrupt pin is enabled, it takes time for the internal pullup to reach a logic 1. Therefore, a false interrupt can occur as soon as the pin is enabled. To prevent a false interrupt on keyboard initialization: 1. Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register. 2. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register. 3. Write to the ACKK bit in the keyboard status and control register to clear any false interrupts. 4. Clear the IMASKK bit. An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load.
MC68HC908GZ8 MOTOROLA Keyboard Interrupt Module (KBI)
Data Sheet 141
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Keyboard Interrupt Module (KBI)
Another way to avoid a false interrupt: 1. Configure the keyboard pins as outputs by setting the appropriate DDRA bits in data direction register A. 2. Write logic 1s to the appropriate port A data register bits. 3. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register.
13.5 Low-Power Modes
The WAIT and STOP instructions put the microcontroller unit (MCU) in low power-consumption standby modes.
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13.5.1 Wait Mode The keyboard module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode. 13.5.2 Stop Mode The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode.
13.6 Keyboard Module During Break Interrupts
The system integration module (SIM) controls whether the keyboard interrupt latch can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. To allow software to clear the keyboard interrupt latch during a break interrupt, write a logic 1 to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the latch during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state has no effect. See 13.7.1 Keyboard Status and Control Register.
13.7 I/O Registers
These registers control and monitor operation of the keyboard module: * * Keyboard status and control register (INTKBSCR) Keyboard interrupt enable register (INTKBIER)
Data Sheet 142 Keyboard Interrupt Module (KBI)
MC68HC908GZ8 MOTOROLA
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Keyboard Interrupt Module (KBI) I/O Registers
13.7.1 Keyboard Status and Control Register The keyboard status and control register: * * * * Flags keyboard interrupt requests Acknowledges keyboard interrupt requests Masks keyboard interrupt requests Controls keyboard interrupt triggering sensitivity
Address: $001A Bit 7 6 0 0 5 0 0 4 0 0 3 KEYF 0 2 0 ACKK 0 0 = Unimplemented 1 IMASKK 0 Bit 0 MODEK 0 Read: Write: Reset: 0
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Figure 13-3. Keyboard Status and Control Register (INTKBSCR) Bits 7-4 -- Not used These read-only bits always read as logic 0s. KEYF -- Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending. Reset clears the KEYF bit. 1 = Keyboard interrupt pending 0 = No keyboard interrupt pending ACKK -- Keyboard Acknowledge Bit Writing a logic 1 to this write-only bit clears the keyboard interrupt request. ACKK always reads as logic 0. Reset clears ACKK. IMASKK -- Keyboard Interrupt Mask Bit Writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. Reset clears the IMASKK bit. 1 = Keyboard interrupt requests masked 0 = Keyboard interrupt requests not masked MODEK -- Keyboard Triggering Sensitivity Bit This read/write bit controls the triggering sensitivity of the keyboard interrupt pins. Reset clears MODEK. 1 = Keyboard interrupt requests on falling edges and low levels 0 = Keyboard interrupt requests on falling edges only
MC68HC908GZ8 MOTOROLA Keyboard Interrupt Module (KBI)
Data Sheet 143
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Keyboard Interrupt Module (KBI)
13.7.2 Keyboard Interrupt Enable Register The keyboard interrupt enable register enables or disables each port A pin to operate as a keyboard interrupt pin.
Address: $001B Bit 7 Read: Write: Reset: KBIE7 0 6 KBIE6 0 5 KBIE5 0 4 KBIE4 0 3 KBIE3 0 2 KBIE2 0 1 KBIE1 0 Bit 0 KBIE0 0
Figure 13-4. Keyboard Interrupt Enable Register (INTKBIER)
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KBIE7-KBIE0 -- Keyboard Interrupt Enable Bits Each of these read/write bits enables the corresponding keyboard interrupt pin to latch interrupt requests. Reset clears the keyboard interrupt enable register. 1 = PTAx pin enabled as keyboard interrupt pin 0 = PTAx pin not enabled as keyboard interrupt pin
Data Sheet 144 Keyboard Interrupt Module (KBI)
MC68HC908GZ8 MOTOROLA
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Data Sheet -- MC68HC908GZ8
Section 14. Low-Voltage Inhibit (LVI)
14.1 Introduction
This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the VDD pin and can force a reset when the VDD voltage falls below the LVI trip falling voltage, VTRIPF.
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14.2 Features
Features of the LVI module include: * * * Programmable LVI reset Selectable LVI trip voltage Programmable stop mode operation
14.3 Functional Description
Figure 14-1 shows the structure of the LVI module. The LVI is enabled out of reset. The LVI module contains a bandgap reference circuit and comparator. Clearing the LVI power disable bit, LVIPWRD, enables the LVI to monitor VDD voltage. Clearing the LVI reset disable bit, LVIRSTD, enables the LVI module to generate a reset when VDD falls below a voltage, VTRIPF. Setting the LVI enable in stop mode bit, LVISTOP, enables the LVI to operate in stop mode. Setting the LVI 5-V or 3-V trip point bit, LVI5OR3, enables the trip point voltage, VTRIPF, to be configured for 5-V operation. Clearing the LVI5OR3 bit enables the trip point voltage, VTRIPF, to be configured for 3-V operation. The actual trip points are shown in Section 24. Electrical Specifications. NOTE: After a power-on reset (POR) the LVI's default mode of operation is 3 V. If a 5-V system is used, the user must set the LVI5OR3 bit to raise the trip point to 5-V operation. Note that this must be done after every power-on reset since the default will revert back to 3-V mode after each power-on reset. If the VDD supply is below the 5-V mode trip voltage but above the 3-V mode trip voltage when POR is released, the part will operate because VTRIPF defaults to 3-V mode after a POR. So, in a 5-V system care must be taken to ensure that VDD is above the 5-V mode trip voltage after POR is released. If the user requires 5-V mode and sets the LVI5OR3 bit after a power-on reset while the VDD supply is not above the VTRIPR for 5-V mode, the microcontroller unit (MCU) will immediately go into reset. The LVI in this case will hold the part in reset
MC68HC908GZ8 MOTOROLA Low-Voltage Inhibit (LVI)
Data Sheet 145
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Low-Voltage Inhibit (LVI)
until either VDD goes above the rising 5-V trip point, VTRIPR, which will release reset or VDD decreases to approximately 0 V which will re-trigger the power-on reset and reset the trip point to 3-V operation. LVISTOP, LVIPWRD, LVI5OR3, and LVIRSTD are in the configuration register (CONFIG1). See Figure 8-2. Configuration Register 1 (CONFIG1) for details of the LVI's configuration bits. Once an LVI reset occurs, the MCU remains in reset until VDD rises above a voltage, VTRIPR, which causes the MCU to exit reset. See 20.3.2.5 Low-Voltage Inhibit (LVI) Reset for details of the interaction between the SIM and the LVI. The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR).
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An LVI reset also drives the RST pin low to provide low-voltage protection to external peripheral devices.
VDD STOP INSTRUCTION LVISTOP FROM CONFIG1 FROM CONFIG1 LVIRSTD LVIPWRD FROM CONFIG LOW VDD DETECTOR VDD > LVITrip = 0 VDD LVITrip = 1 LVIOUT LVI5OR3 FROM CONFIG1 LVI RESET
Figure 14-1. LVI Module Block Diagram
Addr. Register Name Bit 7 LVIOUT 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0
Read: LVI Status Register (LVISR) $FE0C Write: See page 147. Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-2. LVI I/O Register Summary
Data Sheet 146 Low-Voltage Inhibit (LVI)
MC68HC908GZ8 MOTOROLA
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Low-Voltage Inhibit (LVI) LVI Status Register
14.3.1 Polled LVI Operation In applications that can operate at VDD levels below the VTRIPF level, software can monitor VDD by polling the LVIOUT bit. In the configuration register, the LVIPWRD bit must be at logic 0 to enable the LVI module, and the LVIRSTD bit must be at logic 1 to disable LVI resets. 14.3.2 Forced Reset Operation In applications that require VDD to remain above the VTRIPF level, enabling LVI resets allows the LVI module to reset the MCU when VDD falls below the VTRIPF level. In the configuration register, the LVIPWRD and LVIRSTD bits must be at logic 0 to enable the LVI module and to enable LVI resets. 14.3.3 Voltage Hysteresis Protection Once the LVI has triggered (by having VDD fall below VTRIPF), the LVI will maintain a reset condition until VDD rises above the rising trip point voltage, VTRIPR. This prevents a condition in which the MCU is continually entering and exiting reset if VDD is approximately equal to VTRIPF. VTRIPR is greater than VTRIPF by the hysteresis voltage, VHYS. 14.3.4 LVI Trip Selection The LVI5OR3 bit in the configuration register selects whether the LVI is configured for 5-V or 3-V protection. NOTE: The microcontroller is guaranteed to operate at a minimum supply voltage. The trip point (VTRIPF [5 V] or VTRIPF [3 V]) may be lower than this. See Section 24. Electrical Specifications for the actual trip point voltages.
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14.4 LVI Status Register
The LVI status register (LVISR) indicates if the VDD voltage was detected below the VTRIPF level.
Address: Read: Write: Reset: 0 0 = Unimplemented 0 0 0 0 0 0 $FE0C Bit 7 LVIOUT 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 0
Figure 14-3. LVI Status Register (LVISR)
MC68HC908GZ8 MOTOROLA Low-Voltage Inhibit (LVI)
Data Sheet 147
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Low-Voltage Inhibit (LVI)
LVIOUT -- LVI Output Bit This read-only flag becomes set when the VDD voltage falls below the VTRIPF trip voltage (see Table 14-1). Reset clears the LVIOUT bit. Table 14-1. LVIOUT Bit Indication
VDD VDD > VTRIPR VDD < VTRIPF VTRIPF < VDD < VTRIPR LVIOUT 0 1 Previous value
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14.5 LVI Interrupts
The LVI module does not generate interrupt requests.
14.6 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-consumption standby modes. 14.6.1 Wait Mode If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode. 14.6.2 Stop Mode If enabled in stop mode (LVISTOP set), the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode.
Data Sheet 148 Low-Voltage Inhibit (LVI)
MC68HC908GZ8 MOTOROLA
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Data Sheet -- MC68HC908GZ8
Section 15. Monitor ROM (MON)
15.1 Introduction
This section describes the monitor ROM (MON) and the monitor mode entry methods. The monitor ROM allows complete testing of the microcontroller unit (MCU) through a single-wire interface with a host computer. Monitor mode entry can be achieved without use of the higher test voltage, VTST, as long as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for in-circuit programming.
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15.2 Features
Features of the monitor ROM include: * Normal user-mode pin functionality * One pin dedicated to serial communication between monitor read-only memory (ROM) and host computer * Standard mark/space non-return-to-zero (NRZ) communication with host computer * Standard communication baud rate (7200 @ 8-MHz bus frequency) * Execution of code in random-access memory (RAM) or FLASH * FLASH memory security feature(1) * FLASH memory programming interface * 350 bytes monitor ROM code size ($FE20 to $FF7D) * Monitor mode entry without high voltage, VTST, if reset vector is blank ($FFFE and $FFFF contain $FF) * Normal monitor mode entry if high voltage is applied to IRQ
15.3 Functional Description
Figure 15-1 shows a simplified diagram of the monitor mode. The monitor ROM receives and executes commands from a host computer. Figure 15-2 and Figure 15-3 show example circuits used to enter monitor mode and communicate with a host computer via a standard RS-232 interface.
1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908GZ8 MOTOROLA Monitor ROM (MON) Data Sheet 149
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Monitor ROM (MON)
POR RESET
NO
IRQ = VTST?
YES
CONDITIONS FROM Table 15-1
PTA0 = 1, PTA1 = 0, RESET VECTOR BLANK? YES
NO
PTA0 = 1, PTA1 = 0, PTB0 = 1, AND PTB1 = 0? YES NORMAL USER MODE NORMAL MONITOR MODE
NO
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FORCED MONITOR MODE
INVALID USER MODE
HOST SENDS 8 SECURITY BYTES
IS RESET POR? NO
YES
YES
ARE ALL SECURITY BYTES CORRECT?
NO
ENABLE FLASH
DISABLE FLASH
MONITOR MODE ENTRY
DEBUGGING AND FLASH PROGRAMMING (IF FLASH IS ENABLED)
EXECUTE MONITOR CODE
YES
DOES RESET OCCUR?
NO
Figure 15-1. Simplified Monitor Mode Entry Flowchart
Data Sheet 150 Monitor ROM (MON)
MC68HC908GZ8 MOTOROLA
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Monitor ROM (MON) Functional Description
MC68HC908GZ8 N.C. 47 pF OSC2 MAX232 1 1 F + 3 4 C1+ VCC 16 + C1- C2+ GND 15 V+ 2 V- 6 + DB9 2 3 5 7 8 10 9 74HC125 3 2 1 1 F 74HC125 5 6 4 10 k PTA0 PTA1 VSSA VSS VDD 9.1 V PTB1 1 F 1 F + 1 k IRQ VDD 27 pF 8 MHz 10 M OSC1 RST
VDD VDD VDDA 0.1 F VDD 10 k PTB4 10 k PTB0 10 k 10 k
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1 F
+ 5 C2-
Figure 15-2. Normal Monitor Mode Circuit
MC68HC908GZ8 N.C. 47 pF OSC2 MAX232 1 1 F + 3 4 1 F + 5 C2- DB9 2 3 5 7 8 10 9 74HC125 3 2 1 C1+ VCC 16 + C1- C2+ GND 15 V+ 2 V- 6 + 1 F 74HC125 5 6 4 10 k PTA0 PTA1 VSSA VSS VDD 1 F 1 F + N.C. IRQ PTB4 PTB0 PTB1 10 k N.C. N.C. N.C. VDD 27 pF 8 MHz 10 M OSC1 RST VDD VDD VDDA 0.1 F
Figure 15-3. Forced Monitor Mode
MC68HC908GZ8 MOTOROLA Monitor ROM (MON)
Data Sheet 151
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Monitor ROM (MON)
Simple monitor commands can access any memory address. In monitor mode, the MCU can execute code downloaded into RAM by a host computer while most MCU pins retain normal operating mode functions. All communication between the host computer and the MCU is through the PTA0 pin. A level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used in a wired-OR configuration and requires a pullup resistor. Table 15-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode may be entered after a power-on reset (POR) and will allow communication at 7200 baud provided one of the following sets of conditions is met:
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*
If $FFFE and $FFFF does not contain $FF (programmed state): - The external clock is 4 MHz (7200 baud) - PTB4 = low - IRQ = VTST If $FFFE and $FFFF do not contain $FF (programmed state): - The external clock is 8 MHz (7200 baud) - PTB4 = high - IRQ = VTST If $FFFE and $FFFF contain $FF (erased state): - The external clock is 8 MHz (7200 baud) - IRQ = VDD (this can be implemented through the internal IRQ pullup) or VSS
*
*
Enter monitor mode with pin configuration shown in Table 15-1 by pulling RST low and then high. The rising edge of RST latches monitor mode. Once monitor mode is latched, the values on the specified pins can change. Once out of reset, the MCU waits for the host to send eight security bytes (see 15.4 Security). After the security bytes, the MCU sends a break signal (10 consecutive logic 0s) to the host, indicating that it is ready to receive a command.
Data Sheet 152 Monitor ROM (MON)
MC68HC908GZ8 MOTOROLA
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Table 15-1. Monitor Mode Signal Requirements and Options
Serial Communication Divider PLL PTB4 X 0 OFF Disabled 4 MHz 2 MHz 7200 X X X X X Reset condition External Clock Bus Frequency Baud Rate COP Comments PTA0 X 1 0 1 0 X X X PTA1 PTB0 PTB1 Mode Selection Communication Speed
MOTOROLA Reset Vector X X X 1 0 1 0 1 OFF Disabled 8 MHz 2 MHz 7200 $FF (blank) 1 0 X X X OFF Disabled 8 MHz Not $FF X X X X X X Enabled X 2 MHz 7200 X X -- COM [8] -- -- SSEL [10] MOD0 MOD1 [12] [14] DIV4 [16] OSC1 [13] -- -- 1 3 5 7 9 11 13 15 16 14 PTB1 PTB4 12 PTB0 10 PTA1 8 PTA0 6 IRQ 4 RST 2 GND
MC68HC908GZ8
Mode
IRQ
RST
--
X
GND
VTST
Normal Monitor
VDD or VTST
VTST
VDD or VTST
Forced Monitor
VDD or GND
VDD
User
VDD VDD or or GND VTST
Monitor ROM (MON)
MON08 Function [Pin No.]
VTST [6]
RST [4]
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1. PTA0 must have a pullup resistor to VDD in monitor mode. 2. Communication speed in the table is an example to obtain a baud rate of 7200. Baud rate using external oscillator is bus frequency / 278. 3. External clock is an 4 MHz or 8 MHz crystal on OSC1 and OSC2 or a canned oscillator on OSC1. 4. X = don't care 5. MON08 pin refers to P&E Microcomputer Systems' MON08-Cyclone 2 by 8-pin connector.
NC
NC
NC
NC
NC
NC
OSC1
Monitor ROM (MON) Functional Description
Data Sheet
VDD
153
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Monitor ROM (MON)
15.3.1 Normal Monitor Mode If VTST is applied to IRQ and PTB4 is low upon monitor mode entry, the bus frequency is a divide-by-two of the input clock. If PTB4 is high with VTST applied to IRQ upon monitor mode entry, the bus frequency will be a divide-by-four of the input clock. Holding the PTB4 pin low when entering monitor mode causes a bypass of a divide-by-two stage at the oscillator only if VTST is applied to IRQ. In this event, the CGMOUT frequency is equal to the CGMXCLK frequency, and the OSC1 input directly generates internal bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at maximum bus frequency. When monitor mode was entered with VTST on IRQ, the computer operating properly (COP) is disabled as long as VTST is applied to either IRQ or RST. This condition states that as long as VTST is maintained on the IRQ pin after entering monitor mode, or if VTST is applied to RST after the initial reset to get into monitor mode (when VTST was applied to IRQ), then the COP will be disabled. In the latter situation, after VTST is applied to the RST pin, VTST can be removed from the IRQ pin in the interest of freeing the IRQ for normal functionality in monitor mode. 15.3.2 Forced Monitor Mode If entering monitor mode without high voltage on IRQ, then all port B pin requirements and conditions, including the PTB4 frequency divisor selection, are not in effect. This is to reduce circuit requirements when performing in-circuit programming. NOTE: If the reset vector is blank and monitor mode is entered, the chip will see an additional reset cycle after the initial power-on reset (POR). Once the reset vector has been programmed, the traditional method of applying a voltage, VTST, to IRQ must be used to enter monitor mode. An external oscillator of 8 MHz is required for a baud rate of 7200, as the internal bus frequency is automatically set to the external frequency divided by four. When the forced monitor mode is entered the COP is always disabled regardless of the state of IRQ or RST. 15.3.3 Monitor Vectors In monitor mode, the MCU uses different vectors for reset, SWI (software interrupt), and break interrupt than those for user mode. The alternate vectors are in the $FE page instead of the $FF page and allow code execution from the internal monitor firmware instead of user code. Table 15-2 summarizes the differences between user mode and monitor mode.
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Data Sheet 154 Monitor ROM (MON)
MC68HC908GZ8 MOTOROLA
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Monitor ROM (MON) Functional Description
Table 15-2. Mode Differences
Functions Modes User Monitor Reset Vector High $FFFE $FEFE Reset Vector Low $FFFF $FEFF Break Vector High $FFFC $FEFC Break Vector Low $FFFD $FEFD SWI Vector High $FFFC $FEFC SWI Vector Low $FFFD $FEFD
15.3.4 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. Transmit and receive baud rates must be identical.
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START BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
STOP BIT
NEXT START BIT
Figure 15-4. Monitor Data Format 15.3.5 Break Signal A start bit (logic 0) followed by nine logic 0 bits is a break signal. When the monitor receives a break signal, it drives the PTA0 pin high for the duration of approximately two bits and then echoes back the break signal.
MISSING STOP BIT APPROXIMATELY 2 BITS DELAY BEFORE ZERO ECHO
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Figure 15-5. Break Transaction 15.3.6 Baud Rate The communication baud rate is controlled by the crystal frequency or external clock and the state of the PTB4 pin (when IRQ is set to VTST) upon entry into monitor mode. If monitor mode was entered with VDD on IRQ and the reset vector blank, then the baud rate is independent of PTB4. Table 15-1 also lists external frequencies required to achieve a standard baud rate of 7200 bps. The effective baud rate is the bus frequency divided by 278. If using a crystal as the clock source, be aware of the upper frequency limit that the internal clock module can handle. See 24.7 5.0-Volt Control Timing or 24.8 3.3-Volt Control Timing for this limit.
MC68HC908GZ8 MOTOROLA Monitor ROM (MON)
Data Sheet 155
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Monitor ROM (MON)
15.3.7 Commands The monitor ROM firmware uses these commands: * * * * * * READ (read memory) WRITE (write memory) IREAD (indexed read) IWRITE (indexed write) READSP (read stack pointer) RUN (run user program)
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The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit delay at the end of each command allows the host to send a break character to cancel the command. A delay of two bit times occurs before each echo and before READ, IREAD, or READSP data is returned. The data returned by a read command appears after the echo of the last byte of the command. NOTE: Wait one bit time after each echo before sending the next byte.
FROM HOST
READ
READ
ADDRESS HIGH
ADDRESS HIGH
ADDRESS LOW
ADDRESS LOW
DATA
4 ECHO
1
4
1
4
1
3, 2
4 RETURN
Notes: 1 = Echo delay, approximately 2 bit times 2 = Data return delay, approximately 2 bit times 3 = Cancel command delay, 11 bit times 4 = Wait 1 bit time before sending next byte.
Figure 15-6. Read Transaction
FROM HOST
WRITE 3 ECHO 1
WRITE 3
ADDRESS HIGH
ADDRESS HIGH
ADDRESS LOW
ADDRESS LOW
DATA
DATA
1
3
1
3
1
2, 3
Notes: 1 = Echo delay, approximately 2 bit times 2 = Cancel command delay, 11 bit times 3 = Wait 1 bit time before sending next byte.
Figure 15-7. Write Transaction
Data Sheet 156 Monitor ROM (MON)
MC68HC908GZ8 MOTOROLA
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Monitor ROM (MON) Functional Description
A brief description of each monitor mode command is given in Table 15-3 through Table 15-8. Table 15-3. READ (Read Memory) Command
Description Operand Data Returned Opcode Read byte from memory 2-byte address in high-byte:low-byte order Returns contents of specified address $4A Command Sequence
SENT TO MONITOR
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READ
READ
ADDRESS HIGH
ADDRESS HIGH
ADDRESS LOW
ADDRESS LOW
DATA
ECHO
RETURN
Table 15-4. WRITE (Write Memory) Command
Description Operand Data Returned Opcode
FROM HOST
Write byte to memory 2-byte address in high-byte:low-byte order; low byte followed by data byte None $49 Command Sequence
WRITE
WRITE
ADDRESS HIGH
ADDRESS
HIGH
ADDRESS LOW
ADDRESS LOW
DATA
DATA
ECHO
Table 15-5. IREAD (Indexed Read) Command
Description Operand Data Returned Opcode Read next 2 bytes in memory from last address accessed 2-byte address in high byte:low byte order Returns contents of next two addresses $1A Command Sequence
FROM HOST
IREAD
IREAD
DATA
DATA
ECHO
RETURN
MC68HC908GZ8 MOTOROLA Monitor ROM (MON)
Data Sheet 157
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Monitor ROM (MON)
Table 15-6. IWRITE (Indexed Write) Command
Description Operand Data Returned Opcode Write to last address accessed + 1 Single data byte None $19 Command Sequence
FROM HOST
IWRITE
IWRITE
DATA
DATA
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ECHO
A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full 64-Kbyte memory map. Table 15-7. READSP (Read Stack Pointer) Command
Description Operand Data Returned Opcode Reads stack pointer None Returns incremented stack pointer value (SP + 1) in high-byte:low-byte order $0C Command Sequence
FROM HOST
READSP
READSP
SP HIGH
SP LOW
ECHO
RETURN
Table 15-8. RUN (Run User Program) Command
Description Operand Data Returned Opcode Executes PULH and RTI instructions None None $28 Command Sequence
FROM HOST
RUN
RUN
ECHO
Data Sheet 158 Monitor ROM (MON)
MC68HC908GZ8 MOTOROLA
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Monitor ROM (MON) Security
The MCU executes the SWI and PSHH instructions when it enters monitor mode. The RUN command tells the MCU to execute the PULH and RTI instructions. Before sending the RUN command, the host can modify the stacked CPU registers to prepare to run the host program. The READSP command returns the incremented stack pointer value, SP + 1. The high and low bytes of the program counter are at addresses SP + 5 and SP + 6.
SP HIGH BYTE OF INDEX REGISTER CONDITION CODE REGISTER SP + 1 SP + 2 SP + 3 SP + 4 SP + 5 SP + 6 SP + 7
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ACCUMULATOR LOW BYTE OF INDEX REGISTER HIGH BYTE OF PROGRAM COUNTER LOW BYTE OF PROGRAM COUNTER
Figure 15-8. Stack Pointer at Monitor Mode Entry
15.4 Security
A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6-$FFFD. Locations $FFF6-$FFFD contain user-defined data. NOTE: Do not leave locations $FFF6-$FFFD blank. For security reasons, program locations $FFF6-$FFFD even if they are not used for vectors. During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security bytes on pin PTA0. If the received bytes match those at locations $FFF6-$FFFD, the host bypasses the security feature and can read all FLASH locations and execute code from FLASH. Security remains bypassed until a power-on reset occurs. If the reset was not a power-on reset, security remains bypassed and security code entry is not required. See Figure 15-9. Upon power-on reset, if the received bytes of the security code do not match the data at locations $FFF6-$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but reading a FLASH location returns an invalid value and trying to execute code from FLASH causes an illegal address reset. After receiving the eight security bytes from the host, the MCU transmits a break character, signifying that it is ready to receive a command. NOTE: The MCU does not transmit a break character until after the host sends the eight security bytes.
MC68HC908GZ8 MOTOROLA Monitor ROM (MON)
Data Sheet 159
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Monitor ROM (MON)
VDD 4096 + 32 CGMXCLK CYCLES RST COMMAND 1 BYTE 2 ECHO BYTE 8 ECHO 2 BREAK 4 1 COMMAND ECHO
BYTE 1
BYTE 2
FROM HOST PA0 5 FROM MCU 1 BYTE 1 ECHO 4 1
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Notes: 1 = Echo delay, approximately 2 bit times 2 = Data return delay, approximately 2 bit times 4 = Wait 1 bit time before sending next byte 5 = Wait until the monitor ROM runs
Figure 15-9. Monitor Mode Entry Timing To determine whether the security code entered is correct, check to see if bit 6 of RAM address $40 is set. If it is, then the correct security code has been entered and FLASH can be accessed. If the security sequence fails, the device should be reset by a power-on reset and brought up in monitor mode to attempt another entry. After failing the security sequence, the FLASH module can also be mass erased by executing an erase routine that was downloaded into internal RAM. The mass erase operation clears the security code locations so that all eight security bytes become $FF (blank).
Data Sheet 160 Monitor ROM (MON)
BYTE 8
MC68HC908GZ8 MOTOROLA
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Data Sheet -- MC68HC908GZ8
Section 16. MSCAN08 Controller (MSCAN08)
16.1 Introduction
The MSCAN08 is the specific implementation of the Motorola scalable controller area network (MSCAN) concept targeted for the Motorola M68HC08 Microcontroller Family. The module is a communication controller implementing the CAN 2.0 A/B protocol as defined in the BOSCH specification dated September, 1991. The CAN protocol was primarily, but not exclusively, designed to be used as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the electromagnetic interference (EMI) environment of a vehicle, cost-effectiveness, and required bandwidth. MSCAN08 utilizes an advanced buffer arrangement, resulting in a predictable real-time behavior, and simplifies the application software.
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16.2 Features
Basic features of the MSCAN08 are: * * * MSCAN08 enable is software controlled by bit (MSCANEN) in configuration register (CONFIG2) Modular architecture Implementation of the CAN Protocol -- Version 2.0A/B - Standard and extended data frames - 0-8 bytes data length. - Programmable bit rate up to 1 Mbps depending on the actual bit timing and the clock jitter of the phase-locked loop (PLL) Support for remote frames Double-buffered receive storage scheme Triple-buffered transmit storage scheme with internal prioritization using a "local priority" concept Flexible maskable identifier filter supports alternatively one full size extended identifier filter or two 16-bit filters or four 8-bit filters Programmable wakeup functionality with integrated low-pass filter Programmable loop-back mode supports self-test operation
Data Sheet MSCAN08 Controller (MSCAN08) 161
* * * * * *
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MSCAN08 Controller (MSCAN08)
* * * * Separate signalling and interrupt capabilities for all CAN receiver and transmitter error states (warning, error passive, bus off) Programmable MSCAN08 clock source either CPU bus clock or crystal oscillator output Programmable link to timer interface module 2 channel 0 for time-stamping and network synchronization Low-power sleep mode
16.3 External Pins
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The MSCAN08 uses two external pins, one input (CANRx) and one output (CANTx). The CANTx output pin represents the logic level on the CAN: 0 is for a dominant state, and 1 is for a recessive state. A typical CAN system with MSCAN08 is shown in Figure 16-1.
CAN STATION 1 CAN NODE 1 CAN NODE 2 CAN NODE N
MCU
CAN CONTROLLER (MSCAN08)
CANTx
CANRx
TRANSCEIVER
CAN_H
CAN_L C A N BUS
Figure 16-1. The CAN System
Data Sheet 162 MSCAN08 Controller (MSCAN08)
MC68HC908GZ8 MOTOROLA
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MSCAN08 Controller (MSCAN08) Message Storage
Each CAN station is connected physically to the CAN bus lines through a transceiver chip. The transceiver is capable of driving the large current needed for the CAN and has current protection against defected CAN or defected stations.
16.4 Message Storage
MSCAN08 facilitates a sophisticated message storage system which addresses the requirements of a broad range of network applications. 16.4.1 Background
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Modern application layer software is built under two fundamental assumptions: 1. Any CAN node is able to send out a stream of scheduled messages without releasing the bus between two messages. Such nodes will arbitrate for the bus right after sending the previous message and will only release the bus in case of lost arbitration. 2. The internal message queue within any CAN node is organized as such that the highest priority message will be sent out first if more than one message is ready to be sent. Above behavior cannot be achieved with a single transmit buffer. That buffer must be reloaded right after the previous message has been sent. This loading process lasts a definite amount of time and has to be completed within the inter-frame sequence (IFS) to be able to send an uninterrupted stream of messages. Even if this is feasible for limited CAN bus speeds, it requires that the CPU reacts with short latencies to the transmit interrupt. A double buffer scheme would de-couple the re-loading of the transmit buffers from the actual message being sent and as such reduces the reactiveness requirements on the CPU. Problems may arise if the sending of a message would be finished just while the CPU re-loads the second buffer. In that case, no buffer would then be ready for transmission and the bus would be released. At least three transmit buffers are required to meet the first of the above requirements under all circumstances. The MSCAN08 has three transmit buffers. The second requirement calls for some sort of internal prioritization which the MSCAN08 implements with the "local priority" concept described in 16.4.2 Receive Structures. 16.4.2 Receive Structures The received messages are stored in a 2-stage input first in first out (FIFO). The two message buffers are mapped using a "ping pong" arrangement into a single memory area (see Figure 16-2). While the background receive buffer (RxBG) is exclusively associated to the MSCAN08, the foreground receive buffer (RxFG) is addressable by the central processor unit (CPU08). This scheme simplifies the handler software, because only one address area is applicable for the receive process.
MC68HC908GZ8 MOTOROLA MSCAN08 Controller (MSCAN08) Data Sheet 163
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MSCAN08 Controller (MSCAN08)
MSCAN08
RxBG RxFG
CPU08 I BUS
RXF
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Tx0
TXE
PRIO
Tx1
TXE
PRIO
Tx2
TXE
PRIO
Figure 16-2. User Model for Message Buffer Organization
Data Sheet 164 MSCAN08 Controller (MSCAN08)
MC68HC908GZ8 MOTOROLA
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MSCAN08 Controller (MSCAN08) Message Storage
Both buffers have a size of 13 bytes to store the CAN control bits, the identifier (standard or extended), and the data content. For details, see 16.12 Programmer's Model of Message Storage. The receiver full flag (RXF) in the MSCAN08 receiver flag register (CRFLG), signals the status of the foreground receive buffer. When the buffer contains a correctly received message with matching identifier, this flag is set. See 16.13.5 MSCAN08 Receiver Flag Register (CRFLG) On reception, each message is checked to see if it passes the filter (for details see 16.5 Identifier Acceptance Filter) and in parallel is written into RxBG. The MSCAN08 copies the content of RxBG into RxFG(1), sets the RXF flag, and generates a receive interrupt to the CPU(2). The user's receive handler has to read the received message from RxFG and to reset the RXF flag to acknowledge the interrupt and to release the foreground buffer. A new message which can follow immediately after the IFS field of the CAN frame, is received into RxBG. The overwriting of the background buffer is independent of the identifier filter function. When the MSCAN08 module is transmitting, the MSCAN08 receives its own messages into the background receive buffer, RxBG. It does NOT overwrite RxFG, generate a receive interrupt or acknowledge its own messages on the CAN bus. The exception to this rule is in loop-back mode (see 16.13.2 MSCAN08 Module Control Register 1), where the MSCAN08 treats its own messages exactly like all other incoming messages. The MSCAN08 receives its own transmitted messages in the event that it loses arbitration. If arbitration is lost, the MSCAN08 must be prepared to become the receiver. An overrun condition occurs when both the foreground and the background receive message buffers are filled with correctly received messages with accepted identifiers and another message is correctly received from the bus with an accepted identifier. The latter message will be discarded and an error interrupt with overrun indication will be generated if enabled. The MSCAN08 is still able to transmit messages with both receive message buffers filled, but all incoming messages are discarded. 16.4.3 Transmit Structures The MSCAN08 has a triple transmit buffer scheme to allow multiple messages to be set up in advance and to achieve an optimized real-time performance. The three buffers are arranged as shown in Figure 16-2. All three buffers have a 13-byte data structure similar to the outline of the receive buffers (see 16.12 Programmer's Model of Message Storage). An additional transmit buffer priority register (TBPR) contains an 8-bit "local priority" field (PRIO) (see 16.12.5 Transmit Buffer Priority Registers).
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1. Only if the RXF flag is not set. 2. The receive interrupt will occur only if not masked. A polling scheme can be applied on RXF also. MC68HC908GZ8 MOTOROLA MSCAN08 Controller (MSCAN08) Data Sheet 165
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MSCAN08 Controller (MSCAN08)
To transmit a message, the CPU08 has to identify an available transmit buffer which is indicated by a set transmit buffer empty (TXE) flag in the MSCAN08 transmitter flag register (CTFLG) (see 16.13.7 MSCAN08 Transmitter Flag Register). The CPU08 then stores the identifier, the control bits and the data content into one of the transmit buffers. Finally, the buffer has to be flagged ready for transmission by clearing the TXE flag. The MSCAN08 then will schedule the message for transmission and will signal the successful transmission of the buffer by setting the TXE flag. A transmit interrupt is generated(1) when TXE is set and can be used to drive the application software to re-load the buffer. In case more than one buffer is scheduled for transmission when the CAN bus becomes available for arbitration, the MSCAN08 uses the local priority setting of the three buffers for prioritization. For this purpose, every transmit buffer has an 8-bit local priority field (PRIO). The application software sets this field when the message is set up. The local priority reflects the priority of this particular message relative to the set of messages being emitted from this node. The lowest binary value of the PRIO field is defined as the highest priority. The internal scheduling process takes place whenever the MSCAN08 arbitrates for the bus. This is also the case after the occurrence of a transmission error. When a high priority message is scheduled by the application software, it may become necessary to abort a lower priority message being set up in one of the three transmit buffers. As messages that are already under transmission cannot be aborted, the user has to request the abort by setting the corresponding abort request flag (ABTRQ) in the transmission control register (CTCR). The MSCAN08 will then grant the request, if possible, by setting the corresponding abort request acknowledge (ABTAK) and the TXE flag in order to release the buffer and by generating a transmit interrupt. The transmit interrupt handler software can tell from the setting of the ABTAK flag whether the message was actually aborted (ABTAK = 1) or sent (ABTAK = 0).
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16.5 Identifier Acceptance Filter
The identifier acceptance registers (CIDAR0-CIDAR3) define the acceptance patterns of the standard or extended identifier (ID10-ID0 or ID28-ID0). Any of these bits can be marked `don't care' in the identifier mask registers (CIDMR0-CIDMR3). A filter hit is indicated to the application on software by a set RXF (receive buffer full flag, see 16.13.5 MSCAN08 Receiver Flag Register (CRFLG)) and two bits in the identifier acceptance control register (see 16.13.9 MSCAN08 Identifier
1. The transmit interrupt will occur only if not masked. A polling scheme can be applied on TXE also. Data Sheet 166 MSCAN08 Controller (MSCAN08) MC68HC908GZ8 MOTOROLA
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MSCAN08 Controller (MSCAN08) Identifier Acceptance Filter
Acceptance Control Register). These identifier hit flags (IDHIT1 and IDHIT0) clearly identify the filter section that caused the acceptance. They simplify the application software's task to identify the cause of the receiver interrupt. In case that more than one hit occurs (two or more filters match) the lower hit has priority. A very flexible programmable generic identifier acceptance filter has been introduced to reduce the CPU interrupt loading. The filter is programmable to operate in four different modes: 1. Single identifier acceptance filter, each to be applied to a) the full 29 bits of the extended identifier and to the following bits of the CAN frame: RTR, IDE, SRR or b) the 11 bits of the standard identifier plus the RTR and IDE bits of CAN 2.0A/B messages. This mode implements a single filter for a full length CAN 2.0B compliant extended identifier. Figure 16-3 shows how the 32-bit filter bank (CIDAR0-3, CIDMR0-3) produces a filter 0 hit. 2. Two identifier acceptance filters, each to be applied to: a. The 14 most significant bits of the extended identifier plus the SRR and the IDE bits of CAN2.0B messages, or b. The 11 bits of the identifier plus the RTR and IDE bits of CAN 2.0A/B messages. Figure 16-4 shows how the 32-bit filter bank (CIDAR0-CIDAR3 and CIDMR0-CIDMR3) produces filter 0 and 1 hits. 3. Four identifier acceptance filters, each to be applied to the first eight bits of the identifier. This mode implements four independent filters for the first eight bits of a CAN 2.0A/B compliant standard identifier. Figure 16-5 shows how the 32-bit filter bank (CIDAR0-CIDAR3 and CIDMR0-CIDMR3) produces filter 0 to 3 hits. 4. Closed filter. No CAN message will be copied into the foreground buffer RxFG, and the RXF flag will never be set.
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MC68HC908GZ8 MOTOROLA
Data Sheet MSCAN08 Controller (MSCAN08) 167
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MSCAN08 Controller (MSCAN08)
ID28 ID10
IDR0 IDR0
ID21 ID20 ID3 ID2
IDR1 IDR1
ID15 ID14 IDE ID10
IDR2 IDR2
ID7 ID6 ID3 ID10
IDR3 IDR3
RTR ID3
AM7
CIDMR0
AM0 AM7
CIDMR1
AM0 AM7
CIDMR2
AM0 AM7
CIDMR3
AM0
AC7
CIDAR0
AC0 AC7
CIDAR1
AC0 AC7
CIDAR2
AC0 AC7
CIDAR3
AC0
ID Accepted (Filter 0 Hit)
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Figure 16-3. Single 32-Bit Maskable Identifier Acceptance Filter
ID28 ID10
IDR0 IDR0
ID21 ID20 ID3 ID2
IDR1 IDR1
ID15 ID14 IDE ID10
IDR2 IDR2
ID7 ID6 ID3 ID10
IDR3 IDR3
RTR ID3
AM7
CIDMR0
AM0 AM7
CIDMR1
AM0
AC7
CIDAR0
AC0 AC7
CIDAR1
AC0
ID ACCEPTED (FILTER 0 HIT)
AM7
CIDMR2
AM0 AM7
CIDMR3
AM0
AC7
CIDAR2
AC0 AC7
CIDAR3
AC0
ID ACCEPTED (FILTER 1 HIT)
Figure 16-4. Dual 16-Bit Maskable Acceptance Filters
Data Sheet 168 MSCAN08 Controller (MSCAN08)
MC68HC908GZ8 MOTOROLA
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MSCAN08 Controller (MSCAN08) Identifier Acceptance Filter
ID28 ID10
IDR0 IDR0
ID21 ID20 ID3 ID2
IDR1 IDR1
ID15 ID14 IDE ID10
IDR2 IDR2
ID7 ID6 ID3 ID10
IDR3 IDR3
RTR ID3
AM7
CIDMR0
AM0
AC7
CIDAR0
AC0
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ID ACCEPTED (FILTER 0 HIT)
AM7
CIDMR1
AM0
AC7
CIDAR1
AC0
ID ACCEPTED (FILTER 1 HIT)
AM7
CIDMR2
AM0
AC7
CIDAR2
AC0
ID ACCEPTED (FILTER 2 HIT)
AM7
CIDMR3
AM0
AC7
CIDAR3
AC0
ID ACCEPTED (FILTER 3 HIT)
Figure 16-5. Quadruple 8-Bit Maskable Acceptance Filters
MC68HC908GZ8 MOTOROLA MSCAN08 Controller (MSCAN08)
Data Sheet 169
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MSCAN08 Controller (MSCAN08)
16.6 Interrupts
The MSCAN08 supports four interrupt vectors mapped onto eleven different interrupt sources, any of which can be individually masked. For details, see 16.13.5 MSCAN08 Receiver Flag Register (CRFLG) through 16.13.8 MSCAN08 Transmitter Control Register. 1. Transmit Interrupt: At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. The TXE flags of the empty message buffers are set. 2. Receive Interrupt: A message has been received successfully and loaded into the foreground receive buffer. This interrupt will be emitted immediately after receiving the EOF symbol. The RXF flag is set. 3. Wakeup Interrupt: An activity on the CAN bus occurred during MSCAN08 internal sleep mode or power-down mode (provided SLPAK = WUPIE = 1). 4. Error Interrupt: An overrun, error, or warning condition occurred. The receiver flag register (CRFLG) will indicate one of the following conditions: - Overrun: An overrun condition as described in 16.4.2 Receive Structures, has occurred. - Receiver Warning: The receive error counter has reached the CPU warning limit of 96. - Transmitter Warning: The transmit error counter has reached the CPU warning limit of 96. - Receiver Error Passive: The receive error counter has exceeded the error passive limit of 127 and MSCAN08 has gone to error passive state. - Transmitter Error Passive: The transmit error counter has exceeded the error passive limit of 127 and MSCAN08 has gone to error passive state. - Bus Off: The transmit error counter has exceeded 255 and MSCAN08 has gone to bus off state. 16.6.1 Interrupt Acknowledge Interrupts are directly associated with one or more status flags in either the MSCAN08 receiver flag register (CRFLG) or the MSCAN08 transmitter flag register (CTFLG). Interrupts are pending as long as one of the corresponding flags is set. The flags in the above registers must be reset within the interrupt handler in order to handshake the interrupt. The flags are reset through writing a `1' to the corresponding bit position. A flag cannot be cleared if the respective condition still prevails. NOTE: Bit manipulation instructions (BSET) shall not be used to clear interrupt flags.
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Data Sheet 170 MSCAN08 Controller (MSCAN08)
MC68HC908GZ8 MOTOROLA
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MSCAN08 Controller (MSCAN08) Protocol Violation Protection
16.6.2 Interrupt Vectors The MSCAN08 supports four interrupt vectors as shown in Table 16-1. The vector addresses and the relative interrupt priority are dependent on the chip integration and to be defined. Table 16-1. MSCAN08 Interrupt Vector Addresses
Function Wakeup Source WUPIF RWRNIF Local Mask WUPIE RWRNIE TWRNIE RERRIE TERRIE BOFFIE OVRIE RXFIE TXEIE0 TXEIE1 TXEIE2 I bit Global Mask
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TWRNIF RERRIF Error interrupts TERRIF BOFFIF OVRIF Receive RXF TXE0 Transmit TXE1 TXE2
16.7 Protocol Violation Protection
The MSCAN08 will protect the user from accidentally violating the CAN protocol through programming errors. The protection logic implements the following features: * * The receive and transmit error counters cannot be written or otherwise manipulated. All registers which control the configuration of the MSCAN08 can not be modified while the MSCAN08 is on-line. The SFTRES bit in the MSCAN08 module control register (see 16.13.1 MSCAN08 Module Control Register 0) serves as a lock to protect the following registers: - MSCAN08 module control register 1 (CMCR1) - MSCAN08 bus timing register 0 and 1 (CBTR0 and CBTR1) - MSCAN08 identifier acceptance control register (CIDAC) - MSCAN08 identifier acceptance registers (CIDAR0-3) - MSCAN08 identifier mask registers (CIDMR0-3) The CANTx pin is forced to recessive when the MSCAN08 is in any of the low-power modes.
*
MC68HC908GZ8 MOTOROLA MSCAN08 Controller (MSCAN08)
Data Sheet 171
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MSCAN08 Controller (MSCAN08)
16.8 Low-Power Modes
In addition to normal mode, the MSCAN08 has three modes with reduced power consumption: sleep, soft reset, and power down. In sleep and soft reset mode, power consumption is reduced by stopping all clocks except those to access the registers. In power-down mode, all clocks are stopped and no power is consumed. The WAIT and STOP instructions put the MCU in low-power consumption stand-by modes. Table 16-2 summarizes the combinations of MSCAN08 and CPU modes. A particular combination of modes is entered for the given settings of the bits SLPAK and SFTRES. For all modes, an MSCAN08 wakeup interrupt can occur only if SLPAK = WUPIE = 1. . Table 16-2. MSCAN08 versus CPU Operating Modes
CPU Mode MSCAN08 Mode STOP Power Down Sleep Soft Reset Normal 1. `X' means don't care. SLPAK = X(1) SFTRES = X SLPAK = 1 SFTRES = 0 SLPAK = 0 SFTRES = 1 SLPAK = 0 SFTRES = 0 WAIT or RUN
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16.8.1 MSCAN08 Sleep Mode The CPU can request the MSCAN08 to enter the low-power mode by asserting the SLPRQ bit in the module configuration register (see Figure 16-6). The time when the MSCAN08 enters sleep mode depends on its activity: * * * NOTE: If it is transmitting, it continues to transmit until there is no more message to be transmitted, and then goes into sleep mode If it is receiving, it waits for the end of this message and then goes into sleep mode If it is neither transmitting or receiving, it will immediately go into sleep mode
The application software must avoid setting up a transmission (by clearing or more TXE flags) and immediately request sleep mode (by setting SLPRQ). It then depends on the exact sequence of operations whether MSCAN08 starts transmitting or goes into sleep mode directly.
Data Sheet 172 MSCAN08 Controller (MSCAN08)
MC68HC908GZ8 MOTOROLA
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MSCAN08 Controller (MSCAN08) Low-Power Modes
During sleep mode, the SLPAK flag is set. The application software should use SLPAK as a handshake indication for the request (SLPRQ) to go into sleep mode. When in sleep mode, the MSCAN08 stops its internal clocks. However, clocks to allow register accesses still run. If the MSCAN08 is in bus-off state, it stops counting the 128*11 consecutive recessive bits due to the stopped clocks. The CANTx pin stays in recessive state. If RXF = 1, the message can be read and RXF can be cleared. Copying of RxGB into RxFG doesn't take place while in sleep mode. It is possible to access the transmit buffers and to clear the TXE flags. No message abort takes place while in sleep mode. The MSCAN08 leaves sleep mode (wakes-up) when: * Bus activity occurs, or The MCU clears the SLPRQ bit, or The MCU sets the SFTRES bit
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* *
MSCAN08 RUNNING MCU or MSCAN08 SLPRQ = 0 SLPAK = 0 MCU
MSCAN08 SLEEPING SLPRQ = 1 SLPAK = 1
SLEEP REQUEST SLPRQ = 1 SLPAK = 0
MSCAN08
Figure 16-6. Sleep Request/Acknowledge Cycle NOTE: The MCU cannot clear the SLPRQ bit before the MSCAN08 is in sleep mode (SLPAK=1). After wakeup, the MSCAN08 waits for 11 consecutive recessive bits to synchronize to the bus. As a consequence, if the MSCAN08 is woken-up by a CAN frame, this frame is not received. The receive message buffers (RxFG and RxBG) contain messages if they were received before sleep mode was entered. All pending actions are executed upon wakeup: copying of RxBG into RxFG, message aborts and message transmissions. If the MSCAN08 is still in bus-off state after sleep mode was left, it continues counting the 128*11 consecutive recessive bits.
MC68HC908GZ8 MOTOROLA MSCAN08 Controller (MSCAN08)
Data Sheet 173
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Freescale Semiconductor, Inc.
MSCAN08 Controller (MSCAN08)
16.8.2 MSCAN08 Soft Reset Mode In soft reset mode, the MSCAN08 is stopped. Registers can still be accessed. This mode is used to initialize the module configuration, bit timing and the CAN message filter. See 16.13.1 MSCAN08 Module Control Register 0 for a complete description of the soft reset mode. When setting the SFTRES bit, the MSCAN08 immediately stops all ongoing transmissions and receptions, potentially causing CAN protocol violations. NOTE: The user is responsible to take care that the MSCAN08 is not active when soft reset mode is entered. The recommended procedure is to bring the MSCAN08 into sleep mode before the SFTRES bit is set.
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16.8.3 MSCAN08 Power-Down Mode The MSCAN08 is in power-down mode when the CPU is in stop mode. When entering the power-down mode, the MSCAN08 immediately stops all ongoing transmissions and receptions, potentially causing CAN protocol violations. NOTE: The user is responsible to take care that the MSCAN08 is not active when power-down mode is entered. The recommended procedure is to bring the MSCAN08 into sleep mode before the STOP instruction is executed. To protect the CAN bus system from fatal consequences resulting from violations of the above rule, the MSCAN08 drives the CANTx pin into recessive state. In power-down mode, no registers can be accessed. MSCAN08 bus activity can wake the MCU from CPU stop/MSCAN08 power-down mode. However, until the oscillator starts up and synchronization is achieved the MSCAN08 will not respond to incoming data. 16.8.4 CPU Wait Mode The MSCAN08 module remains active during CPU wait mode. The MSCAN08 will stay synchronized to the CAN bus and generates transmit, receive, and error interrupts to the CPU, if enabled. Any such interrupt will bring the MCU out of wait mode. 16.8.5 Programmable Wakeup Function The MSCAN08 can be programmed to apply a low-pass filter function to the CANRx input line while in internal sleep mode (see information on control bit WUPM in 16.13.2 MSCAN08 Module Control Register 1). This feature can be used to protect the MSCAN08 from wakeup due to short glitches on the CAN bus lines. Such glitches can result from electromagnetic inference within noisy environments.
Data Sheet 174 MSCAN08 Controller (MSCAN08)
MC68HC908GZ8 MOTOROLA
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MSCAN08 Controller (MSCAN08) Timer Link
16.9 Timer Link
The MSCAN08 will generate a timer signal whenever a valid frame has been received. Because the CAN specification defines a frame to be valid if no errors occurred before the EOF field has been transmitted successfully, the timer signal will be generated right after the EOF. A pulse of one bit time is generated. As the MSCAN08 receiver engine also receives the frames being sent by itself, a timer signal also will be generated after a successful transmission. The previously described timer signal can be routed into the on-chip 2-channel timer interface module 2 (TIM2). This signal is connected to TIM2 channel 0 input under the control of the timer link enable (TLNKEN) bit in CMCR0.
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After the timer has been programmed to capture rising edge events, it can be used under software control to generate 16-bit time stamps which can be stored with the received message.
16.10 Clock System
Figure 16-7 shows the structure of the MSCAN08 clock generation circuitry and its interaction with the clock generation module (CGM). With this flexible clocking scheme the MSCAN08 is able to handle CAN bus rates ranging from 10 kbps up to 1 Mbps.
CGMXCLK OSC /2 CGMOUT (TO SIM) BCS PLL /2
CGM MSCAN08 (2 * BUS FREQUENCY) /2 MSCANCLK PRESCALER CLKSRC (1 ... 64)
Figure 16-7. Clocking Scheme
MC68HC908GZ8 MOTOROLA MSCAN08 Controller (MSCAN08)
Data Sheet 175
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Freescale Semiconductor, Inc.
MSCAN08 Controller (MSCAN08)
The clock source bit (CLKSRC) in the MSCAN08 module control register (CMCR1) (see 16.13.1 MSCAN08 Module Control Register 0) defines whether the MSCAN08 is connected to the output of the crystal oscillator or to the PLL output. The clock source has to be chosen such that the tight oscillator tolerance requirements (up to 0.4%) of the CAN protocol are met. NOTE: If the system clock is generated from a PLL, it is recommended to select the crystal clock source rather than the system clock source due to jitter considerations, especially at faster CAN bus rates. A programmable prescaler is used to generate out of the MSCAN08 clock the time quanta (Tq) clock. A time quantum is the atomic unit of time handled by the MSCAN08. fTq = fMSCANCLK Presc value
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A bit time is subdivided into three segments(1) (see Figure 16-8): * * SYNC_SEG: This segment has a fixed length of one time quantum. Signal edges are expected to happen within this section. Time segment 1: This segment includes the PROP_SEG and the PHASE_SEG1 of the CAN standard. It can be programmed by setting the parameter TSEG1 to consist of 4 to 16 time quanta. Time segment 2: This segment represents PHASE_SEG2 of the CAN standard. It can be programmed by setting the TSEG2 parameter to be 2 to 8 time quanta long. fTq Bit rate = No. of time quanta
*
The synchronization jump width (SJW) can be programmed in a range of 1 to 4 time quanta by setting the SJW parameter. The above parameters can be set by programming the bus timing registers, CBTR0 and CBTR1. See 16.13.3 MSCAN08 Bus Timing Register 0 and 16.13.4 MSCAN08 Bus Timing Register 1. NOTE: It is the user's responsibility to make sure that the bit timing settings are in compliance with the CAN standard, Table 16-8 gives an overview on the CAN conforming segment settings and the related parameter values.
1. For further explanation of the underlying concepts please refer to ISO/DIS 11 519-1, Section 10.3. Data Sheet 176 MSCAN08 Controller (MSCAN08) MC68HC908GZ8 MOTOROLA
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MSCAN08 Controller (MSCAN08) Clock System
NRZ SIGNAL
SYNC _SEG 1
TIME SEGMENT 1 (PROP_SEG + PHASE_SEG1) 4 ... 16 8... 25 TIME QUANTA = 1 BIT TIME
TIME SEG. 2 (PHASE_SEG2) 2 ... 8
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SAMPLE POINT (SINGLE OR TRIPLE SAMPLING)
Figure 16-8. Segments Within the Bit Time
Table 16-3. Time Segment Syntax
SYNC_SEG Transmit point System expects transitions to occur on the bus during this period. A node in transmit mode will transfer a new value to the CAN bus at this point. A node in receive mode will sample the bus at this point. If the three samples per bit option is selected then this point marks the position of the third sample.
Sample point
Table 16-4. CAN Standard Compliant Bit Time Segment Settings
Time Segment 1 5 .. 10 4 .. 11 5 .. 12 6 .. 13 7 .. 14 8 .. 15 9 .. 16 TSEG1 4 .. 9 3 .. 10 4 .. 11 5 .. 12 6 .. 13 7 .. 14 8 .. 15 Time Segment 2 2 3 4 5 6 7 8 TSEG2 1 2 3 4 5 6 7 Synchronized Jump Width 1 .. 2 1 .. 3 1 .. 4 1 .. 4 1 .. 4 1 .. 4 1 .. 4 SJW 0 .. 1 0 .. 2 0 .. 3 0 .. 3 0 .. 3 0 .. 3 0 .. 3
MC68HC908GZ8 MOTOROLA MSCAN08 Controller (MSCAN08)
Data Sheet 177
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MSCAN08 Controller (MSCAN08)
16.11 Memory Map
The MSCAN08 occupies 128 bytes in the CPU08 memory space. The absolute mapping is implementation dependent with the base address being a multiple of 128.
$0500 $0508 $0509 $050D CONTROL REGISTERS 9 BYTES RESERVED 5 BYTES ERROR COUNTERS 2 BYTES IDENTIFIER FILTER 8 BYTES RESERVED 40 BYTES RECEIVE BUFFER $054F $0550 TRANSMIT BUFFER 0 $055F $0560 TRANSMIT BUFFER 1 $056F $0570 TRANSMIT BUFFER 2 $057F
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$050E $050F $0510 $0517 $0518 $053F $0540
Figure 16-9. MSCAN08 Memory Map
Data Sheet 178 MSCAN08 Controller (MSCAN08)
MC68HC908GZ8 MOTOROLA
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MSCAN08 Controller (MSCAN08) Programmer's Model of Message Storage
16.12 Programmer's Model of Message Storage
This section details the organization of the receive and transmit message buffers and the associated control registers. For reasons of programmer interface simplification, the receive and transmit message buffers have the same outline. Each message buffer allocates 16 bytes in the memory map containing a 13-byte data structure. An additional transmit buffer priority register (TBPR) is defined for the transmit buffers.
Addr(1) $05b0 Register Name IDENTIFIER REGISTER 0 IDENTIFIER REGISTER 1 IDENTIFIER REGISTER 2 IDENTIFIER REGISTER 3 DATA SEGMENT REGISTER 0 DATA SEGMENT REGISTER 1 DATA SEGMENT REGISTER 2 DATA SEGMENT REGISTER 3 DATA SEGMENT REGISTER 4 DATA SEGMENT REGISTER 5 DATA SEGMENT REGISTER 6 DATA SEGMENT REGISTER 7 DATA LENGTH REGISTER TRANSMIT BUFFER PRIORITY REGISTER(2) UNUSED UNUSED
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$05b1 $05b2 $05b3 $05b4 $05b5 $05b6 $05b7 $05b8 $05b9 $05bA $05bB $05bC $05bD $05bE $05bF
1. Where b equals the following: b=4 for receive buffer b=5 for transmit buffer 0 b=6 for transmit buffer 1 b=7 for transmit buffer 2 2. Not applicable for receive buffers
Figure 16-10. Message Buffer Organization
MC68HC908GZ8 MOTOROLA MSCAN08 Controller (MSCAN08)
Data Sheet 179
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Freescale Semiconductor, Inc.
MSCAN08 Controller (MSCAN08)
16.12.1 Message Buffer Outline Figure 16-11 shows the common 13-byte data structure of receive and transmit buffers for extended identifiers. The mapping of standard identifiers into the IDR registers is shown in Figure 16-12. All bits of the 13-byte data structure are undefined out of reset. NOTE: The foreground receive buffer can be read anytime but cannot be written. The transmit buffers can be read or written anytime.
Addr.
Register IDR0 Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
Bit 7 ID28
6 ID27
5 ID26
4 ID25
3 ID24
2 ID23
1 ID22
Bit 0 ID21
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$05b0
$05b1
IDR1
ID20
ID19
ID18
SRR (=1)
IDE (=1)
ID17
ID16
ID15
$05b2
IDR2
ID14
ID13
ID12
ID11
ID10
ID9
ID8
ID7
$05b3
IDR3
ID6
ID5
ID4
ID3
ID2
ID1
ID0
RTR
$05b4
DSR0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
$05b5
DSR1
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
$05b6
DSR2
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
$05b7
DSR3
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
$05b8
DSR4
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
$05b9
DSR5
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
= Unimplemented
Figure 16-11. Receive/Transmit Message Buffer Extended Identifier (IDRn)
Data Sheet 180 MSCAN08 Controller (MSCAN08) MC68HC908GZ8 MOTOROLA
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MSCAN08 Controller (MSCAN08) Programmer's Model of Message Storage
Addr.
Register Read: Write: Read: Write: Read: Write:
Bit 7
6
5
4
3
2
1
Bit 0
$05bA
DSR6
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
$05bB
DSR7
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
$05bC
DLR
DLC3
DLC2
DLC1
DLC0
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= Unimplemented
Figure 16-11. Receive/Transmit Message Buffer Extended Identifier (IDRn) (Continued)
Addr. $05b0
Register IDR0 Read: Write: Read: Write: Read: Write: Read: Write:
Bit 7 ID10
6 ID9
5 ID8
4 ID7
3 ID6
2 ID5
1 ID4
Bit 0 ID3
$05b1
IDR1
ID2
ID1
ID0
RTR
IDE (=0)
$05b2
IDR2
$05b3
IDR3
= Unimplemented
Figure 16-12. Standard Identifier Mapping 16.12.2 Identifier Registers The identifiers consist of either 11 bits (ID10-ID0) for the standard, or 29 bits (ID28-ID0) for the extended format. ID10/28 is the most significant bit and is transmitted first on the bus during the arbitration procedure. The priority of an identifier is defined to be highest for the smallest binary number. SRR -- Substitute Remote Request This fixed recessive bit is used only in extended format. It must be set to 1 by the user for transmission buffers and will be stored as received on the CAN bus for receive buffers.
MC68HC908GZ8 MOTOROLA MSCAN08 Controller (MSCAN08)
Data Sheet 181
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MSCAN08 Controller (MSCAN08)
IDE -- ID Extended This flag indicates whether the extended or standard identifier format is applied in this buffer. In case of a receive buffer, the flag is set as being received and indicates to the CPU how to process the buffer identifier registers. In case of a transmit buffer, the flag indicates to the MSCAN08 what type of identifier to send. 1 = Extended format, 29 bits 0 = Standard format, 11 bits RTR -- Remote Transmission Request This flag reflects the status of the remote transmission request bit in the CAN frame. In case of a receive buffer, it indicates the status of the received frame and supports the transmission of an answering frame in software. In case of a transmit buffer, this flag defines the setting of the RTR bit to be sent. 1 = Remote frame 0 = Data frame 16.12.3 Data Length Register (DLR) This register keeps the data length field of the CAN frame. DLC3-DLC0 -- Data Length Code Bits The data length code contains the number of bytes (data byte count) of the respective message. At transmission of a remote frame, the data length code is transmitted as programmed while the number of transmitted bytes is always 0. The data byte count ranges from 0 to 8 for a data frame. Table 16-5 shows the effect of setting the DLC bits. Table 16-5. Data Length Codes
Data Length Code DLC3 0 0 0 0 0 0 0 0 1 DLC2 0 0 0 0 1 1 1 1 0 DLC1 0 0 1 1 0 0 1 1 0 DLC0 0 1 0 1 0 1 0 1 0 Data Byte Count 0 1 2 3 4 5 6 7 8
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16.12.4 Data Segment Registers (DSRn) The eight data segment registers contain the data to be transmitted or received. The number of bytes to be transmitted or being received is determined by the data length code in the corresponding DLR.
Data Sheet 182 MSCAN08 Controller (MSCAN08)
MC68HC908GZ8 MOTOROLA
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MSCAN08 Controller (MSCAN08) Programmer's Model of Control Registers
16.12.5 Transmit Buffer Priority Registers
Address: Read: Write: Reset: $05bD Bit 7 PRIO7 6 PRIO6 5 PRIO5 4 PRIO4 3 PRIO3 2 PRIO2 1 PRIO1 Bit 0 PRIO0
Unaffected by reset
Figure 16-13. Transmit Buffer Priority Register (TBPR) PRIO7-PRIO0 -- Local Priority This field defines the local priority of the associated message buffer. The local priority is used for the internal prioritization process of the MSCAN08 and is defined to be highest for the smallest binary number. The MSCAN08 implements the following internal prioritization mechanism: * * * All transmission buffers with a cleared TXE flag participate in the prioritization right before the SOF is sent. The transmission buffer with the lowest local priority field wins the prioritization. In case more than one buffer has the same lowest priority, the message buffer with the lower index number wins.
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16.13 Programmer's Model of Control Registers
The programmer's model has been laid out for maximum simplicity and efficiency. Figure 16-14 gives an overview on the control register block of the MSCAN08.
Addr. $0500 Register CMCR0 Read: Write: Read: Write: Read: Write: Read: Write: 0 0 0 0 Bit 7 0 6 0 5 0 4 SYNCH 3 TLNKEN 2 SLPAK 1 SLPRQ Bit 0 SFTRES
$0501
CMCR1
0
LOOPB
WUPM
CLKSRC
$0502
CBTR0
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
$0503
CBTR1
SAMP
TSEG22
TSEG21
TSEG20
TSEG13
TSEG12
TSEG11
TSEG10
= Unimplemented
R
= Reserved
Figure 16-14. MSCAN08 Control Register Structure (Sheet 1 of 3)
MC68HC908GZ8 MOTOROLA MSCAN08 Controller (MSCAN08)
Data Sheet 183
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MSCAN08 Controller (MSCAN08)
Addr. $0504
Register CRFLG Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write: Read: Write:
Bit 7 WUPIF
6 RWRNIF
5 TWRNIF
4 RERRIF
3 TERRIF
2 BOFFIF
1 OVRIF
Bit 0 RXF
$0505
CRIER
WUPIE
RWRNIE
TWRNIE
RERRIE
TERRIE
BOFFIE
OVRIE
RXFIE
$0506
CTFLG
0
ABTAK2
ABTAK1
ABTAK0
0
TXE2
TXE1
TXE0
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$0507
CTCR
0
ABTRQ2
ABTRQ1
ABTRQ0
0
TXEIE2
TXEIE1
TXEIE0
$0508
CIDAC
0
0
IDAM1
IDAM0
0
0
IDHIT1
IDHIT0
$0509
Reserved
R
R
R
R
R
R
R
R
$050E
CRXERR
RXERR7
RXERR6
RXERR5
RXERR4
RXERR3
RXERR2
RXERR1
RXERR0
$050F
CTXERR
TXERR7
TXERR6
TXERR5
TXERR4
TXERR3
TXERR2
TXERR1
TXERR0
$0510
CIDAR0
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
$0511
CIDAR1
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
$0512
CIDAR2
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
$0513
CIDAR3
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
$0514
CIDMR0
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
= Unimplemented
R
= Reserved
Figure 16-14. MSCAN08 Control Register Structure (Sheet 2 of 3)
Data Sheet 184 MSCAN08 Controller (MSCAN08)
MC68HC908GZ8 MOTOROLA
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MSCAN08 Controller (MSCAN08) Programmer's Model of Control Registers
Addr. $0515
Register CIDMR1 Read: Write: Read: Write: Read: Write:
Bit 7 AM7
6 AM6
5 AM5
4 AM4
3 AM3
2 AM2
1 AM1
Bit 0 AM0
$0516
CIDMR2
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
$0517
CIDMR3
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
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= Unimplemented
R
= Reserved
Figure 16-14. MSCAN08 Control Register Structure (Sheet 3 of 3) 16.13.1 MSCAN08 Module Control Register 0
Address: $0500 Bit 7 Read: Write: Reset: 0 0 0 = Unimplemented 0 0 6 0 5 0 4 SYNCH 3 TLNKEN 0 2 SLPAK 0 1 SLPRQ 0 Bit 0 SFTRES 1
Figure 16-15. Module Control Register 0 (CMCR0) SYNCH -- Synchronized Status This bit indicates whether the MSCAN08 is synchronized to the CAN bus and as such can participate in the communication process. 1 = MSCAN08 synchronized to the CAN bus 0 = MSCAN08 not synchronized to the CAN bus TLNKEN -- Timer Enable This flag is used to establish a link between the MSCAN08 and the on-chip timer (see 16.9 Timer Link). 1 = The MSCAN08 timer signal output is connected to the timer input. 0 = The port is connected to the timer input. SLPAK -- Sleep Mode Acknowledge This flag indicates whether the MSCAN08 is in module internal sleep mode. It shall be used as a handshake for the sleep mode request (see 16.8.1 MSCAN08 Sleep Mode). If the MSCAN08 detects bus activity while in sleep mode, it clears the flag. 1 = Sleep - MSCAN08 in internal sleep mode 0 = Wakeup - MSCAN08 is not in sleep mode
MC68HC908GZ8 MOTOROLA MSCAN08 Controller (MSCAN08)
Data Sheet 185
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MSCAN08 Controller (MSCAN08)
SLPRQ -- Sleep Request, Go to Internal Sleep Mode This flag requests the MSCAN08 to go into an internal power-saving mode (see 16.8.1 MSCAN08 Sleep Mode). 1 = Sleep -- The MSCAN08 will go into internal sleep mode. 0 = Wakeup -- The MSCAN08 will function normally. SFTRES -- Soft Reset When this bit is set by the CPU, the MSCAN08 immediately enters the soft reset state. Any ongoing transmission or reception is aborted and synchronization to the bus is lost. The following registers enter and stay in their hard reset state: CMCR0, CRFLG, CRIER, CTFLG, and CTCR. The registers CMCR1, CBTR0, CBTR1, CIDAC, CIDAR0-CIDAR3, and CIDMR0-CIDMR3 can only be written by the CPU when the MSCAN08 is in soft reset state. The values of the error counters are not affected by soft reset. When this bit is cleared by the CPU, the MSCAN08 tries to synchronize to the CAN bus. If the MSCAN08 is not in bus-off state, it will be synchronized after 11 recessive bits on the bus; if the MSCAN08 is in bus-off state, it continues to wait for 128 occurrences of 11 recessive bits. Clearing SFTRES and writing to other bits in CMCR0 must be in separate instructions. 1 = MSCAN08 in soft reset state 0 = Normal operation 16.13.2 MSCAN08 Module Control Register 1
Address: Read: Write: Reset: 0 0 0 = Unimplemented 0 0 $0501 Bit 7 0 6 0 5 0 4 0 3 0 2 LOOPB 0 1 WUPM 0 Bit 0 CLKSRC 0
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Figure 16-16. Module Control Register (CMCR1) LOOPB -- Loop Back Self-Test Mode When this bit is set, the MSCAN08 performs an internal loop back which can be used for self-test operation: the bit stream output of the transmitter is fed back to the receiver internally. The CANRx input pin is ignored and the CANTx output goes to the recessive state (logic 1). The MSCAN08 behaves as it does normally when transmitting and treats its own transmitted message as a message received from a remote node. In this state the MSCAN08 ignores the bit sent during the ACK slot of the CAN frame Acknowledge field to insure proper reception of its own message. Both transmit and receive interrupts are generated. 1 = Activate loop back self-test mode 0 = Normal operation
Data Sheet 186 MSCAN08 Controller (MSCAN08)
MC68HC908GZ8 MOTOROLA
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MSCAN08 Controller (MSCAN08) Programmer's Model of Control Registers
WUPM -- Wakeup Mode This flag defines whether the integrated low-pass filter is applied to protect the MSCAN08 from spurious wakeups (see 16.8.5 Programmable Wakeup Function). 1 = MSCAN08 will wakeup the CPU only in cases of a dominant pulse on the bus which has a length of at least twup. 0 = MSCAN08 will wakeup the CPU after any recessive-to-dominant edge on the CAN bus. CLKSRC -- Clock Source This flag defines which clock source the MSCAN08 module is driven from (see 16.10 Clock System). 1 = The MSCAN08 clock source is CGMOUT (see Figure 16-7). 0 = The MSCAN08 clock source is CGMXCLK/2 (see Figure 16-7). NOTE: The CMCR1 register can be written only if the SFTRES bit in the MSCAN08 module control register is set
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16.13.3 MSCAN08 Bus Timing Register 0
Address: Read: Write: Reset: $0502 Bit 7 SJW1 0 6 SJW0 0 5 BRP5 0 4 BRP4 0 3 BRP3 0 2 BRP2 0 1 BRP1 0 Bit 0 BRP0 0
Figure 16-17. Bus Timing Register 0 (CBTR0) SJW1 and SJW0 -- Synchronization Jump Width The synchronization jump width (SJW) defines the maximum number of time quanta (Tq) clock cycles by which a bit may be shortened, or lengthened, to achieve resynchronization on data transitions on the bus (see Table 16-6). Table 16-6. Synchronization Jump Width
SJW1 0 0 1 1 SJW0 0 1 0 1 Synchronization Jump Width 1 Tq cycle 2 Tq cycle 3 Tq cycle 4 Tq cycle
BRP5-BRP0 -- Baud Rate Prescaler These bits determine the time quanta (Tq) clock, which is used to build up the individual bit timing, according to Table 16-7.
MC68HC908GZ8 MOTOROLA MSCAN08 Controller (MSCAN08)
Data Sheet 187
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MSCAN08 Controller (MSCAN08)
Table 16-7. Baud Rate Prescaler
BRP5 0 0 0 0 : : 1 BRP4 0 0 0 0 : : 1 BRP3 0 0 0 0 : : 1 BRP2 0 0 0 0 : : 1 BRP1 0 0 1 1 : : 1 BRP0 0 1 0 1 : : 1 Prescaler Value (P) 1 2 3 4 : : 64
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NOTE:
The CBTR0 register can be written only if the SFTRES bit in the MSCAN08 module control register is set.
16.13.4 MSCAN08 Bus Timing Register 1
Address: Read: Write: Reset: $0503 Bit 7 SAMP 0 6 TSEG22 0 5 TSEG21 0 4 TSEG20 0 3 TSEG13 0 2 TSEG12 0 1 TSEG11 0 Bit 0 TSEG10 0
Figure 16-18. Bus Timing Register 1 (CBTR1) SAMP -- Sampling This bit determines the number of serial bus samples to be taken per bit time. If set, three samples per bit are taken, the regular one (sample point) and two preceding samples, using a majority rule. For higher bit rates, SAMP should be cleared, which means that only one sample will be taken per bit. 1 = Three samples per bit(1) 0 = One sample per bit TSEG22-TSEG10 -- Time Segment Time segments within the bit time fix the number of clock cycles per bit time and the location of the sample point. Time segment 1 (TSEG1) and time segment 2 (TSEG2) are programmable as shown in Table 16-8. The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time quanta (Tq) clock cycles per bit as shown in Table 16-4). Bit time = NOTE: Pres value fMSCANCLK * number of time quanta
The CBTR1 register can only be written if the SFTRES bit in the MSCAN08 module control register is set.
1. In this case PHASE_SEG1 must be at least 2 time quanta.
Data Sheet 188 MSCAN08 Controller (MSCAN08)
MC68HC908GZ8 MOTOROLA
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MSCAN08 Controller (MSCAN08) Programmer's Model of Control Registers
Table 16-8. Time Segment Values
TSEG13 0 0 0 0 . . TSEG12 0 0 0 0 . . 1 TSEG11 0 0 1 1 . . 1 TSEG10 0 1 0 1 . . 1 Time Segment 1 1 Tq Cycle(1) 2 Tq Cycles(1) 3Tq Cycles(1) 4 Tq Cycles . . 16 Tq Cycles TSEG22 0 0 . . 1 TSEG21 0 0 . . 1 TSEG20 0 1 . . 1 Time Segment 2 1 Tq Cycle(1) 2 Tq Cycles . . 8Tq Cycles
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1
1. This setting is not valid. Please refer to Table 16-4 for valid settings.
16.13.5 MSCAN08 Receiver Flag Register (CRFLG) All bits of this register are read and clear only. A flag can be cleared by writing a 1 to the corresponding bit position. A flag can be cleared only when the condition which caused the setting is valid no more. Writing a 0 has no effect on the flag setting. Every flag has an associated interrupt enable flag in the CRIER register. A hard or soft reset will clear the register.
Address: Read: Write: Reset: $0504 Bit 7 WUPIF 0 6 RWRNIF 0 5 TWRNIF 0 4 RERRIF 0 3 TERRIF 0 2 BOFFIF 0 1 OVRIF 0 Bit 0 RXF 0
Figure 16-19. Receiver Flag Register (CRFLG) WUPIF -- Wakeup Interrupt Flag If the MSCAN08 detects bus activity while in sleep mode, it sets the WUPIF flag. If not masked, a wakeup interrupt is pending while this flag is set. 1 = MSCAN08 has detected activity on the bus and requested wakeup. 0 = No wakeup interrupt has occurred. RWRNIF -- Receiver Warning Interrupt Flag This flag is set when the MSCAN08 goes into warning status due to the receive error counter (REC) exceeding 96 and neither one of the error interrupt flags or the bus-off interrupt flag is set(1). If not masked, an error interrupt is pending while this flag is set. 1 = MSCAN08 has gone into receiver warning status. 0 = No receiver warning status has been reached.
1. Condition to set the flag: RWRNIF = (96 REC) & RERRIF & TERRIF & BOFFIF MC68HC908GZ8 MOTOROLA MSCAN08 Controller (MSCAN08) Data Sheet 189
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MSCAN08 Controller (MSCAN08)
TWRNIF -- Transmitter Warning Interrupt Flag This flag is set when the MSCAN08 goes into warning status due to the transmit error counter (TEC) exceeding 96 and neither one of the error interrupt flags or the bus-off interrupt flag is set(1). If not masked, an error interrupt is pending while this flag is set. 1 = MSCAN08 has gone into transmitter warning status. 0 = No transmitter warning status has been reached. RERRIF -- Receiver Error Passive Interrupt Flag This flag is set when the MSCAN08 goes into error passive status due to the receive error counter exceeding 127 and the bus-off interrupt flag is not set(2). If not masked, an error interrupt is pending while this flag is set. 1 = MSCAN08 has gone into receiver error passive status. 0 = No receiver error passive status has been reached. TERRIF -- Transmitter Error Passive Interrupt Flag This flag is set when the MSCAN08 goes into error passive status due to the transmit error counter exceeding 127 and the bus-off interrupt flag is not set(3). If not masked, an error interrupt is pending while this flag is set. 1 = MSCAN08 went into transmit error passive status. 0 = No transmit error passive status has been reached. BOFFIF -- Bus-Off Interrupt Flag This flag is set when the MSCAN08 goes into bus-off status, due to the transmit error counter exceeding 255. It cannot be cleared before the MSCAN08 has monitored 128 times 11 consecutive `recessive' bits on the bus. If not masked, an error interrupt is pending while this flag is set. 1 = MSCAN08has gone into bus-off status. 0 = No bus-off status has been reached. OVRIF -- Overrun Interrupt Flag This flag is set when a data overrun condition occurs. If not masked, an error interrupt is pending while this flag is set. 1 = A data overrun has been detected since last clearing the flag. 0 = No data overrun has occurred. RXF -- Receive Buffer Full The RXF flag is set by the MSCAN08 when a new message is available in the foreground receive buffer. This flag indicates whether the buffer is loaded with a correctly received message. After the CPU has read that message from the receive buffer the RXF flag must be cleared to release the buffer. A set RXF flag prohibits the exchange of the background receive buffer into the foreground buffer. If not masked, a receive interrupt is pending while this flag is set. 1 = The receive buffer is full. A new message is available. 0 = The receive buffer is released (not full).
1. Condition to set the flag: TWRNIF = (96 TEC) & RERRIF & TERRIF & BOFFIF 2. Condition to set the flag: RERRIF = (127 REC 255) & BOFFIF 3. Condition to set the flag: TERRIF = (128 TEC 255) & BOFFIF Data Sheet 190 MSCAN08 Controller (MSCAN08) MC68HC908GZ8 MOTOROLA
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MSCAN08 Controller (MSCAN08) Programmer's Model of Control Registers
NOTE:
To ensure data integrity, no registers of the receive buffer shall be read while the RXF flag is cleared. The CRFLG register is held in the reset state when the SFTRES bit in CMCR0 is set.
16.13.6 MSCAN08 Receiver Interrupt Enable Register
Address: Read: $0505 Bit 7 Write: Reset: WUPIE 0 6 RWRNIE 0 5 TWRNIE 0 4 RERRIE 0 3 TERRIE 0 2 BOFFIE 0 1 OVRIE 0 Bit 0 RXFIE 0
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Figure 16-20. Receiver Interrupt Enable Register (CRIER) WUPIE -- Wakeup Interrupt Enable 1 = A wakeup event will result in a wakeup interrupt. 0 = No interrupt will be generated from this event. RWRNIE -- Receiver Warning Interrupt Enable 1 = A receiver warning status event will result in an error interrupt. 0 = No interrupt is generated from this event. TWRNIE -- Transmitter Warning Interrupt Enable 1 = A transmitter warning status event will result in an error interrupt. 0 = No interrupt is generated from this event. RERRIE -- Receiver Error Passive Interrupt Enable 1 = A receiver error passive status event will result in an error interrupt. 0 = No interrupt is generated from this event. TERRIE -- Transmitter Error Passive Interrupt Enable 1 = A transmitter error passive status event will result in an error interrupt. 0 = No interrupt is generated from this event. BOFFIE -- Bus-Off Interrupt Enable 1 = A bus-off event will result in an error interrupt. 0 = No interrupt is generated from this event. OVRIE -- Overrun Interrupt Enable 1 = An overrun event will result in an error interrupt. 0 = No interrupt is generated from this event. RXFIE -- Receiver Full Interrupt Enable 1 = A receive buffer full (successful message reception) event will result in a receive interrupt. 0 = No interrupt will be generated from this event. NOTE: The CRIER register is held in the reset state when the SFTRES bit in CMCR0 is set.
MC68HC908GZ8 MOTOROLA MSCAN08 Controller (MSCAN08)
Data Sheet 191
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MSCAN08 Controller (MSCAN08)
16.13.7 MSCAN08 Transmitter Flag Register The abort acknowledge flags are read only. The transmitter buffer empty flags are read and clear only. A flag can be cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect on the flag setting. The transmitter buffer empty flags each have an associated interrupt enable bit in the CTCR register. A hard or soft reset will resets the register.
Address: Read: $0506 Bit 7 0 0 Write: Reset: 0 0 = Unimplemented 0 0 5 6 ABTAK2 5 ABTAK1 4 ABTAK0 3 0 2 TXE2 1 1 TXE1 1 Bit 0 TXE0 1
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Figure 16-21. Transmitter Flag Register (CTFLG) ABTAK2-ABTAK0 -- Abort Acknowledge This flag acknowledges that a message has been aborted due to a pending abort request from the CPU. After a particular message buffer has been flagged empty, this flag can be used by the application software to identify whether the message has been aborted successfully or has been sent. The ABTAKx flag is cleared implicitly whenever the corresponding TXE flag is cleared. 1 = The message has been aborted. 0 = The message has not been aborted, thus has been sent out. TXE2-TXE0 -- Transmitter Empty This flag indicates that the associated transmit message buffer is empty, thus not scheduled for transmission. The CPU must handshake (clear) the flag after a message has been set up in the transmit buffer and is due for transmission. The MSCAN08 sets the flag after the message has been sent successfully. The flag is also set by the MSCAN08 when the transmission request was successfully aborted due to a pending abort request (see 16.12.5 Transmit Buffer Priority Registers). If not masked, a receive interrupt is pending while this flag is set. Clearing a TXEx flag also clears the corresponding ABTAKx flag (ABTAK, see above). When a TXEx flag is set, the corresponding ABTRQx bit (ABTRQ) is cleared. See 16.13.8 MSCAN08 Transmitter Control Register 1 = The associated message buffer is empty (not scheduled). 0 = The associated message buffer is full (loaded with a message due for transmission). NOTE: To ensure data integrity, no registers of the transmit buffers should be written to while the associated TXE flag is cleared. The CTFLG register is held in the reset state when the SFTRES bit in CMCR0 is set.
Data Sheet 192 MSCAN08 Controller (MSCAN08)
MC68HC908GZ8 MOTOROLA
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MSCAN08 Controller (MSCAN08) Programmer's Model of Control Registers
16.13.8 MSCAN08 Transmitter Control Register
Address: Read: Write: Reset: 0 $0507 Bit 7 0 6 ABTRQ2 0 5 ABTRQ1 0 = Unimplemented 4 ABTRQ0 0 3 0 0 2 TXEIE2 0 1 TXEIE1 0 Bit 0 TXEIE0 0
Figure 16-22. Transmitter Control Register (CTCR)
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ABTRQ2-ABTRQ0 -- Abort Request The CPU sets an ABTRQx bit to request that an already scheduled message buffer (TXE = 0) be aborted. The MSCAN08 will grant the request if the message has not already started transmission, or if the transmission is not successful (lost arbitration or error). When a message is aborted the associated TXE and the abort acknowledge flag (ABTAK) (see 16.13.7 MSCAN08 Transmitter Flag Register) will be set and an TXE interrupt is generated if enabled. The CPU cannot reset ABTRQx. ABTRQx is cleared implicitly whenever the associated TXE flag is set. 1 = Abort request pending 0 = No abort request NOTE: The software must not clear one or more of the TXE flags in CTFLG and simultaneously set the respective ABTRQ bit(s). TXEIE2-TXEIE0 -- Transmitter Empty Interrupt Enable 1 = A transmitter empty (transmit buffer available for transmission) event results in a transmitter empty interrupt. 0 = No interrupt is generated from this event. NOTE: The CTCR register is held in the reset state when the SFTRES bit in CMCR0 is set.
MC68HC908GZ8 MOTOROLA MSCAN08 Controller (MSCAN08)
Data Sheet 193
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MSCAN08 Controller (MSCAN08)
16.13.9 MSCAN08 Identifier Acceptance Control Register
Address: Read: Write: Reset: 0 0 $0508 Bit 7 0 6 0 5 IDAM1 0 = Unimplemented 4 IDAM0 0 3 0 0 2 0 0 1 IDHIT1 0 Bit 0 IDHIT0 0
Figure 16-23. Identifier Acceptance Control Register (CIDAC)
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IDAM1-IDAM0-- Identifier Acceptance Mode The CPU sets these flags to define the identifier acceptance filter organization (see 16.5 Identifier Acceptance Filter). Table 16-9 summarizes the different settings. In "filter closed" mode no messages will be accepted so that the foreground buffer will never be reloaded. Table 16-9. Identifier Acceptance Mode Settings
IDAM1 0 0 1 1 IDAM0 0 1 0 1 Identifier Acceptance Mode Single 32-bit acceptance filter Two 16-bit acceptance filter Four 8-bit acceptance filters Filter closed
IDHIT1-IDHIT0-- Identifier Acceptance Hit Indicator The MSCAN08 sets these flags to indicate an identifier acceptance hit (see 16.5 Identifier Acceptance Filter). Table 16-9 summarizes the different settings. Table 16-10. Identifier Acceptance Hit Indication
IDHIT1 0 0 1 1 IDHIT0 0 1 0 1 Identifier Acceptance Hit Filter 0 hit Filter 1 hit Filter 2 hit Filter 3 hit
The IDHIT indicators are always related to the message in the foreground buffer. When a message gets copied from the background to the foreground buffer, the indicators are updated as well. NOTE: The CIDAC register can be written only if the SFTRES bit in the CMCR0 is set.
Data Sheet 194 MSCAN08 Controller (MSCAN08)
MC68HC908GZ8 MOTOROLA
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MSCAN08 Controller (MSCAN08) Programmer's Model of Control Registers
16.13.10 MSCAN08 Receive Error Counter
Address: Read: Write: Reset: 0 0 0 = Unimplemented 0 0 0 0 0 $050E Bit 7 RXERR7 6 RXERR6 5 RXERR5 4 RXERR4 3 RXERR3 2 RXERR2 1 RXERR1 Bit 0 RXERR0
Figure 16-24. Receiver Error Counter (CRXERR)
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This read-only register reflects the status of the MSCAN08 receive error counter. 16.13.11 MSCAN08 Transmit Error Counter
Address: Read: Write: Reset: 0 0 0 = Unimplemented 0 0 0 0 0 $050F Bit 7 TXERR7 6 TXERR6 5 TXERR5 4 TXERR4 3 TXERR3 2 TXERR2 1 TXERR1 Bit 0 TXERR0
Figure 16-25. Transmit Error Counter (CTXERR) This read-only register reflects the status of the MSCAN08 transmit error counter. NOTE: Both error counters may only be read when in sleep or soft reset mode.
MC68HC908GZ8 MOTOROLA MSCAN08 Controller (MSCAN08)
Data Sheet 195
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MSCAN08 Controller (MSCAN08)
16.13.12 MSCAN08 Identifier Acceptance Registers On reception each message is written into the background receive buffer. The CPU is only signalled to read the message, however, if it passes the criteria in the identifier acceptance and identifier mask registers (accepted); otherwise, the message will be overwritten by the next message (dropped). The acceptance registers of the MSCAN08 are applied on the IDR0 to IDR3 registers of incoming messages in a bit by bit manner. For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers only the first two (CIDMR0/CIDMR1 and CIDAR0/CIDAR1) are applied.
CIDAR0 Address: $0510 Bit 7 Read: Write: Reset: CIDAR1 Address: $050511 Bit 7 Read: Write: Reset: CIDAR2 Address: $0512 Bit 7 Read: Write: Reset: CIDAR3 Address: $0513 Bit 7 Read: Write: Reset: AC7 6 AC6 5 AC5 4 AC4 3 AC3 2 AC2 1 AC1 Bit 0 AC0 AC7 6 AC6 5 AC5 4 AC4 3 AC3 2 AC2 1 AC1 Bit 0 AC0 AC7 6 AC6 5 AC5 4 AC4 3 AC3 2 AC2 1 AC1 Bit 0 AC0 AC7 6 AC6 5 AC5 4 AC4 3 AC3 2 AC2 1 AC1 Bit 0 AC0
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Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
Figure 16-26. Identifier Acceptance Registers (CIDAR0-CIDAR3) AC7-AC0 -- Acceptance Code Bits AC7-AC0 comprise a user-defined sequence of bits with which the corresponding bits of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison is then masked with the corresponding identifier mask register. NOTE: The CIDAR0-CIDAR3 registers can be written only if the SFTRES bit in CMCR0 is set
MC68HC908GZ8 MSCAN08 Controller (MSCAN08) MOTOROLA
Data Sheet 196
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MSCAN08 Controller (MSCAN08) Programmer's Model of Control Registers
16.13.13 MSCAN08 Identifier Mask Registers (CIDMR0-CIDMR3) The identifier mask registers specify which of the corresponding bits in the identifier acceptance register are relevant for acceptance filtering. For standard identifiers it is required to program the last three bits (AM2-AM0) in the mask register CIDMR1 to `don't care'.
CIDMRO Address: $0514 Bit 7 Read: Write: Reset: CIDMR1 Address: $0515 Bit 7 Read: Write: Reset: CIDMR2 Address: $0516 Bit 7 Read: Write: Reset: CIDMR3 Address: $0517 Bit 7 Read: Write: Reset: AM7 6 AM6 5 AM5 4 AM4 3 AM3 2 AM2 1 AM1 Bit 0 AM0 AM7 6 AM6 5 AM5 4 AM4 3 AM3 2 AM2 1 AM1 Bit 0 AM0 AM7 6 AM6 5 AM5 4 AM4 3 AM3 2 AM2 1 AM1 Bit 0 AM0 AM7 6 AM6 5 AM5 4 AM4 3 AM3 2 AM2 1 AM1 Bit 0 AM0
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Unaffected by reset
Unaffected by reset
Unaffected by reset
Unaffected by reset
Figure 16-27. Identifier Mask Registers (CIDMR0-CIDMR3) AM7-AM0 -- Acceptance Mask Bits If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier acceptance register must be the same as its identifier bit before a match will be detected. The message will be accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier acceptance register will not affect whether or not the message is accepted. 1 = Ignore corresponding acceptance code register bit. 0 = Match corresponding acceptance code register and identifier bits. NOTE: The CIDMR0-CIDMR3 registers can be written only if the SFTRES bit in the CMCR0 is set
MC68HC908GZ8 MOTOROLA MSCAN08 Controller (MSCAN08)
Data Sheet 197
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MSCAN08 Controller (MSCAN08)
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Data Sheet 198 MSCAN08 Controller (MSCAN08)
MC68HC908GZ8 MOTOROLA
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Data Sheet -- MC68HC908GZ8
Section 17. Input/Output (I/O) Ports
17.1 Introduction
Bidirectional input-output (I/O) pins form five parallel ports. All I/O pins are programmable as inputs or outputs. All individual bits within port A, port C, and port D are software configurable with pullup devices if configured as input port bits. The pullup devices are automatically and dynamically disabled when a port bit is switched to output mode. NOTE: Connect any unused I/O pins to an appropriate logic level, either VDD or VSS. Although the I/O ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. Not all port pins are bonded out in all packages. Care sure be taken to make any unbonded port pins an output to reduce them from being floating inputs.
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Addr.
Register Name Read: Port A Data Register (PTA) Write: See page 202. Reset: Read: Port B Data Register (PTB) Write: See page 204. Reset: Read: Port C Data Register (PTC) Write: See page 207. Reset: Read: Port D Data Register (PTD) Write: See page 210. Reset:
Bit 7 PTA7
6 PTA6
5 PTA5
4 PTA4
3 PTA3
2 PTA2
1 PTA1
Bit 0 PTA0
$0000
Unaffected by reset PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
$0001
Unaffected by reset 1 PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0
$0002
Unaffected by reset PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
$0003
Unaffected by reset = Unimplemented
Figure 17-1. I/O Port Register Summary
MC68HC908GZ8 MOTOROLA Input/Output (I/O) Ports
Data Sheet 199
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Input/Output (I/O) Ports
Addr.
Register Name Read: Data Direction Register A (DDRA) Write: See page 202. Reset: Read: Data Direction Register B (DDRB) Write: See page 205. Reset: Read: Data Direction Register C (DDRC) Write: See page 208. Reset: Read: Data Direction Register D (DDRD) Write: See page 211. Reset: Read: Port E Data Register (PTE) Write: See page 213. Reset: Read: Data Direction Register E (DDRE) Write: See page 214. Reset:
Bit 7 DDRA7 0 DDRB7 0 0
6 DDRA6 0 DDRB6 0 DDRC6
5 DDRA5 0 DDRB5 0 DDRC5 0 DDRD5 0 PTE5
4 DDRA4 0 DDRB4 0 DDRC4 0 DDRD4 0 PTE4
3 DDRA3 0 DDRB3 0 DDRC3 0 DDRD3 0 PTE3
2 DDRA2 0 DDRB2 0 DDRC2 0 DDRD2 0 PTE2
1 DDRA1 0 DDRB1 0 DDRC1 0 DDRD1 0 PTE1
Bit 0 DDRA0 0 DDRB0 0 DDRC0 0 DDRD0 0 PTE0
$0004
$0005
$0006
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0 DDRD7 0 0
0 DDRD6 0 0
$0007
$0008
Unaffected by reset 0 0 DDRE5 0 0 PTAPUE6 0 PTCPUE6 0 0 PTDPUE6 0 = Unimplemented 0 PTAPUE5 0 PTCPUE5 0 PTDPUE5 0 DDRE4 0 PTAPUE4 0 PTCPUE4 0 PTDPUE4 0 DDRE3 0 PTAPUE3 0 PTCPUE3 0 PTDPUE3 0 DDRE2 0 PTAPUE2 0 PTCPUE2 0 PTDPUE2 0 DDRE1 0 PTAPUE1 0 PTCPUE1 0 PTDPUE1 0 DDRE0 0 PTAPUE0 0 PTCPUE0 0 PTDPUE0 0
$000C
$000D
Read: Port A Input Pullup Enable PTAPUE7 Register (PTAPUE) Write: See page 204. Reset: 0 Read: Port C Input Pullup Enable Register (PTCPUE) Write: See page 209. Reset: 0
$000E
$000F
Read: Port D Input Pullup Enable PTDPUE7 Register (PTDPUE) Write: See page 213. Reset: 0
Figure 17-1. I/O Port Register Summary (Continued)
Data Sheet 200 Input/Output (I/O) Ports
MC68HC908GZ8 MOTOROLA
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Input/Output (I/O) Ports Introduction
Table 17-1. Port Control Register Bits Summary
Port Bit 0 1 2 A 3 4 5 6 7 0 1 2 B 3 4 5 6 7 0 1 2 C 3 4 5 6 0 1 2 D 3 4 5 6 7 0 1 E 2 3 4 5 DDR DDRA0 DDRA1 DDRA2 DDRA3 DDRA4 DDRA5 DDRA6 DDRA7 DDRB0 DDRB1 DDRB2 DDRB3 DDRB4 DDRB5 DDRB6 DDRB7 DDRC0 DDRC1 DDRC2 DDRC3 DDRC4 DDRC5 DDRC6 DDRD0 DDRD1 DDRD2 DDRD3 DDRD4 DDRD5 DDRD6 DDRD7 DDRE0 DDRE1 DDRE2 DDRE3 DDRE4 DDRE5 TIM1 TIM2 SCI ELS0B:ELS0A ELS1B:ELS1A ELS0B:ELS0A ELS1B:ELS1A ENSCI SPI SPE MSCAN08 CANEN ADC ADCH4-ADCH0 KBD Module Control KBIE0 KBIE1 KBIE2 KBIE3 KBIE4 KBIE5 KBIE6 KBIE7 Pin PTA0/KBD0 PTA1/KBD1 PTA2/KBD2 PTA3/KBD3 PTA4/KBD4 PTA5/KBD5 PTA6/KBD6 PTA7/KBD7 PTB0/AD0 PTB1/AD1 PTB2/AD2 PTB3/AD3 PTB4/AD4 PTB5/AD5 PTB6/AD6 PTB7/AD7 PTC0 PTC1 PTC2 PTC3 PTC4 PTC5 PTC6 PTD0/SS PTD1/MISO PTD2/MOSI PTD3/SPSCK PTD4/T1CH0 PTD5/T1CH1 PTD6/T2CH0 PTD7/T2CH1 PTE0/TxD PTE1/RxD PTE2 PTE3 PTE4 PTE5
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MC68HC908GZ8 MOTOROLA
Data Sheet Input/Output (I/O) Ports 201
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Input/Output (I/O) Ports
17.2 Port A
Port A is an 8-bit special-function port that shares all eight of its pins with the keyboard interrupt (KBI) module. Port A also has software configurable pullup devices if configured as an input port. 17.2.1 Port A Data Register The port A data register (PTA) contains a data latch for each of the eight port A pins.
Address: $0000 Bit 7 Read: Write: Reset: Alternate Function: KBD7 KBD6 KBD5 PTA7 6 PTA6 5 PTA5 4 PTA4 3 PTA3 2 PTA2 1 PTA1 Bit 0 PTA0
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Unaffected by reset KBD4 KBD3 KBD2 KBD1 KBD0
Figure 17-2. Port A Data Register (PTA) PTA7-PTA0 -- Port A Data Bits These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit in data direction register A. Reset has no effect on port A data. KBD7-KBD0 -- Keyboard Inputs The keyboard interrupt enable bits, KBIE7-KBIE0, in the keyboard interrupt control register (KBICR) enable the port A pins as external interrupt pins. See Section 13. Keyboard Interrupt Module (KBI). 17.2.2 Data Direction Register A Data direction register A (DDRA) determines whether each port A pin is an input or an output. Writing a logic 1 to a DDRA bit enables the output buffer for the corresponding port A pin; a logic 0 disables the output buffer.
Address: Read: Write: Reset: $0004 Bit 7 DDRA7 0 6 DDRA6 0 5 DDRA5 0 4 DDRA4 0 3 DDRA3 0 2 DDRA2 0 1 DDRA1 0 Bit 0 DDRA0 0
Figure 17-3. Data Direction Register A (DDRA)
Data Sheet 202 Input/Output (I/O) Ports
MC68HC908GZ8 MOTOROLA
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Input/Output (I/O) Ports Port A
DDRA7-DDRA0 -- Data Direction Register A Bits These read/write bits control port A data direction. Reset clears DDRA7-DDRA0, configuring all port A pins as inputs. 1 = Corresponding port A pin configured as output 0 = Corresponding port A pin configured as input NOTE: Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from 0 to 1. Figure 17-4 shows the port A I/O logic.
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READ DDRA ($0004)
WRITE DDRA ($0004) RESET WRITE PTA ($0000) VDD PTAPUEx INTERNAL PULLUP DEVICE PTAx PTAx DDRAx
INTERNAL DATA BUS
READ PTA ($0000)
Figure 17-4. Port A I/O Circuit When bit DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 17-2 summarizes the operation of the port A pins. Table 17-2. Port A Pin Functions
PTAPUE Bit 1 0 X DDRA Bit 0 0 1 PTA Bit X(1) X X I/O Pin Mode Input, VDD(2) Input, Hi-Z(4) Output Accesses to DDRA Read/Write DDRA7-DDRA0 DDRA7-DDRA0 DDRA7-DDRA0 Read Pin Pin PTA7-PTA0 Accesses to PTA Write PTA7-PTA0(3) PTA7-PTA0(3) PTA7-PTA0
1. X = Don't care 2. I/O pin pulled up to VDD by internal pullup device 3. Writing affects data register, but does not affect input. 4. Hi-Z = High impedance
MC68HC908GZ8 MOTOROLA Input/Output (I/O) Ports
Data Sheet 203
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Input/Output (I/O) Ports
17.2.3 Port A Input Pullup Enable Register The port A input pullup enable register (PTAPUE) contains a software configurable pullup device for each of the eight port A pins. Each bit is individually configurable and requires that the data direction register, DDRA, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port bit's DDRA is configured for output mode.
Address: Read: $000D Bit 7 Write: Reset: PTAPUE7 0 6 PTAPUE6 0 5 PTAPUE5 0 4 PTAPUE4 0 3 PTAPUE3 0 2 PTAPUE2 0 1 PTAPUE1 0 Bit 0 PTAPUE0 0
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Figure 17-5. Port A Input Pullup Enable Register (PTAPUE) PTAPUE7-PTAPUE0 -- Port A Input Pullup Enable Bits These writable bits are software programmable to enable pullup devices on an input port bit. 1 = Corresponding port A pin configured to have internal pullup 0 = Corresponding port A pin has internal pullup disconnected
17.3 Port B
Port B is an 8-bit special-function port that shares all eight of its pins with the analog-to-digital converter (ADC) module. 17.3.1 Port B Data Register The port B data register (PTB) contains a data latch for each of the eight port pins.
Address: Read: Write: Reset: Alternate Function: AD7 AD6 AD5 $0001 Bit 7 PTB7 6 PTB6 5 PTB5 4 PTB4 3 PTB3 2 PTB2 1 PTB1 Bit 0 PTB0
Unaffected by reset AD4 AD3 AD2 AD1 AD0
Figure 17-6. Port B Data Register (PTB) PTB7-PTB0 -- Port B Data Bits These read/write bits are software-programmable. Data direction of each port B pin is under the control of the corresponding bit in data direction register B. Reset has no effect on port B data.
Data Sheet 204 Input/Output (I/O) Ports
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Input/Output (I/O) Ports Port B
AD7-AD0 -- Analog-to-Digital Input Bits AD7-AD0 are pins used for the input channels to the analog-to-digital converter module. The channel select bits in the ADC status and control register define which port B pin will be used as an ADC input and overrides any control from the port I/O logic by forcing that pin as the input to the analog circuitry. NOTE: Care must be taken when reading port B while applying analog voltages to AD7-AD0 pins. If the appropriate ADC channel is not enabled, excessive current drain may occur if analog voltages are applied to the PTBx/ADx pin, while PTB is read as a digital input. Those ports not selected as analog input channels are considered digital I/O ports.
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17.3.2 Data Direction Register B Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a logic 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0 disables the output buffer.
Address: Read: Write: Reset: $0005 Bit 7 DDRB7 0 6 DDRB6 0 5 DDRB5 0 4 DDRB4 0 3 DDRB3 0 2 DDRB2 0 1 DDRB1 0 Bit 0 DDRB0 0
Figure 17-7. Data Direction Register B (DDRB) DDRB7-DDRB0 -- Data Direction Register B Bits These read/write bits control port B data direction. Reset clears DDRB7-DDRB0, configuring all port B pins as inputs. 1 = Corresponding port B pin configured as output 0 = Corresponding port B pin configured as input NOTE: Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from 0 to 1. Figure 17-8 shows the port B I/O logic.
MC68HC908GZ8 MOTOROLA Input/Output (I/O) Ports
Data Sheet 205
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Input/Output (I/O) Ports
READ DDRB ($0005)
WRITE DDRB ($0005) INTERNAL DATA BUS RESET WRITE PTB ($0001) PTBx PTBx DDRBx
READ PTB ($0001)
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Figure 17-8. Port B I/O Circuit When bit DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When bit DDRBx is a logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 17-3 summarizes the operation of the port B pins. Table 17-3. Port B Pin Functions
DDRB Bit 0 1 PTB Bit X(1) X I/O Pin Mode Input, Hi-Z(2) Output Accesses to DDRB Read/Write DDRB7-DDRB0 DDRB7-DDRB0 Read Pin PTB7-PTB0 Accesses to PTB Write PTB7-PTB0(3) PTB7-PTB0
1. X = Don't care 2. Hi-Z = High impedance 3. Writing affects data register, but does not affect input.
Data Sheet 206 Input/Output (I/O) Ports
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Input/Output (I/O) Ports Port C
17.4 Port C
Port C is a 7-bit, general-purpose bidirectional I/O port. Port C also has software configurable pullup devices if configured as an input port. 17.4.1 Port C Data Register The port C data register (PTC) contains a data latch for each of the seven port C pins. NOTE: Bit 6 through bit 2 of PTC are not available in the 32-pin LQFP package.
Address: Read: Write: Reset: Alternate Function: = Unimplemented $0002 Bit 7 1 6 PTC6 5 PTC5 4 PTC4 3 PTC3 2 PTC2 1 PTC1 Bit 0 PTC0
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Unaffected by reset CANRX CANTX
Figure 17-9. Port C Data Register (PTC) PTC6-PTC0 -- Port C Data Bits These read/write bits are software-programmable. Data direction of each port C pin is under the control of the corresponding bit in data direction register C. Reset has no effect on port C data. CANRX and CANTX -- MSCAN08 Bits The CANRX-CANTX pins are the MSCAN08 modules receive and transmit pins. The CANEN bit in the MSCAN08 control register determines, whether the PTC1/CANRX-PTC0/CANTX pins are MSCAN08 pins or general-purpose I/O pins. See Section 16. MSCAN08 Controller (MSCAN08).
MC68HC908GZ8 MOTOROLA Input/Output (I/O) Ports
Data Sheet 207
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Input/Output (I/O) Ports
17.4.2 Data Direction Register C Data direction register C (DDRC) determines whether each port C pin is an input or an output. Writing a logic 1 to a DDRC bit enables the output buffer for the corresponding port C pin; a logic 0 disables the output buffer.
Address: Read: Write: Reset: 0 $0006 Bit 7 0 6 DDRC6 0 = Unimplemented 5 DDRC5 0 4 DDRC4 0 3 DDRC3 0 2 DDRC2 0 1 DDRC1 0 Bit 0 DDRC0 0
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Figure 17-10. Data Direction Register C (DDRC) DDRC6-DDRC0 -- Data Direction Register C Bits These read/write bits control port C data direction. Reset clears DDRC6-DDRC0, configuring all port C pins as inputs. 1 = Corresponding port C pin configured as output 0 = Corresponding port C pin configured as input NOTE: Avoid glitches on port C pins by writing to the port C data register before changing data direction register C bits from 0 to 1. Figure 17-11 shows the port C I/O logic.
READ DDRC ($0006)
WRITE DDRC ($0006) INTERNAL DATA BUS RESET WRITE PTC ($0002) PTCx VDD PTCPUEx INTERNAL PULLUP DEVICE PTCx DDRCx
READ PTC ($0002)
Figure 17-11. Port C I/O Circuit When bit DDRCx is a logic 1, reading address $0002 reads the PTCx data latch. When bit DDRCx is a logic 0, reading address $0002 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 17-4 summarizes the operation of the port C pins.
Data Sheet 208 Input/Output (I/O) Ports MC68HC908GZ8 MOTOROLA
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Input/Output (I/O) Ports Port C
Table 17-4. Port C Pin Functions
PTCPUE Bit 1 0 X DDRC Bit 0 0 1 PTC Bit X(1) X X I/O Pin Mode Input, VDD(2) Input, Hi-Z(4) Output Accesses to DDRC Read/Write DDRC6-DDRC0 DDRC6-DDRC0 DDRC6-DDRC0 Read Pin Pin PTC6-PTC0 Accesses to PTC Write PTC6-PTC0(3) PTC6-PTC0(3) PTC6-PTC0
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1. X = Don't care 2. I/O pin pulled up to VDD by internal pullup device. 3. Writing affects data register, but does not affect input. 4. Hi-Z = High impedance
17.4.3 Port C Input Pullup Enable Register The port C input pullup enable register (PTCPUE) contains a software configurable pullup device for each of the seven port C pins. Each bit is individually configurable and requires that the data direction register, DDRC, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port bit's DDRC is configured for output mode.
Address: Read: Write: Reset: 0 $000E Bit 7 0 6 PTCPUE6 0 = Unimplemented 5 PTCPUE5 0 4 PTCPUE4 0 3 PTCPUE3 0 2 PTCPUE2 0 1 PTCPUE1 0 Bit 0 PTCPUE0 0
Figure 17-12. Port C Input Pullup Enable Register (PTCPUE) PTCPUE6-PTCPUE0 -- Port C Input Pullup Enable Bits These writable bits are software programmable to enable pullup devices on an input port bit. 1 = Corresponding port C pin configured to have internal pullup 0 = Corresponding port C pin internal pullup disconnected
MC68HC908GZ8 MOTOROLA Input/Output (I/O) Ports
Data Sheet 209
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Input/Output (I/O) Ports
17.5 Port D
Port D is an 8-bit special-function port that shares four of its pins with the serial peripheral interface (SPI) module and four of its pins with two timer interface (TIM1 and TIM2) modules. Port D also has software configurable pullup devices if configured as an input port. 17.5.1 Port D Data Register The port D data register (PTD) contains a data latch for each of the eight port D pins.
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Address: Read: Write: Reset: Alternate Function:
$0003 Bit 7 PTD7 6 PTD6 5 PTD5 4 PTD4 3 PTD3 2 PTD2 1 PTD1 Bit 0 PTD0
Unaffected by reset T2CH1 T2CH0 T1CH1 T1CH0 SPSCK MOSI MISO SS
Figure 17-13. Port D Data Register (PTD) PTD7-PTD0 -- Port D Data Bits These read/write bits are software-programmable. Data direction of each port D pin is under the control of the corresponding bit in data direction register D. Reset has no effect on port D data. T2CH1 and T2CH0 -- Timer 2 Channel I/O Bits The PTD7/T2CH1-PTD6/T2CH0 pins are the TIM2 input capture/output compare pins. The edge/level select bits, ELSxB:ELSxA, determine whether the PTD7/T2CH1-PTD6/T2CH0 pins are timer channel I/O pins or general-purpose I/O pins. See Section 23. Timer Interface Module (TIM). T1CH1 and T1CH0 -- Timer 1 Channel I/O Bits The PTD7/T1CH1-PTD6/T1CH0 pins are the TIM1 input capture/output compare pins. The edge/level select bits, ELSxB and ELSxA, determine whether the PTD7/T1CH1-PTD6/T1CH0 pins are timer channel I/O pins or general-purpose I/O pins. See Section 23. Timer Interface Module (TIM). SPSCK -- SPI Serial Clock The PTD3/SPSCK pin is the serial clock input of the SPI module. When the SPE bit is clear, the PTD3/SPSCK pin is available for general-purpose I/O. MOSI -- Master Out/Slave In The PTD2/MOSI pin is the master out/slave in terminal of the SPI module. When the SPE bit is clear, the PTD2/MOSI pin is available for general-purpose I/O.
Data Sheet 210 Input/Output (I/O) Ports
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Input/Output (I/O) Ports Port D
MISO -- Master In/Slave Out The PTD1/MISO pin is the master in/slave out terminal of the SPI module. When the SPI enable bit, SPE, is clear, the SPI module is disabled, and the PTD0/SS pin is available for general-purpose I/O. Data direction register D (DDRD) does not affect the data direction of port D pins that are being used by the SPI module. However, the DDRD bits always determine whether reading port D returns the states of the latches or the states of the pins. See Table 17-5. SS -- Slave Select The PTD0/SS pin is the slave select input of the SPI module. When the SPE bit is clear, or when the SPI master bit, SPMSTR, is set, the PTD0/SS pin is available for general-purpose I/O. When the SPI is enabled, the DDRB0 bit in data direction register B (DDRB) has no effect on the PTD0/SS pin. 17.5.2 Data Direction Register D Data direction register D (DDRD) determines whether each port D pin is an input or an output. Writing a logic 1 to a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the output buffer.
Address: Read: Write: Reset: $0007 Bit 7 DDRD7 0 6 DDRD6 0 5 DDRD5 0 4 DDRD4 0 3 DDRD3 0 2 DDRD2 0 1 DDRD1 0 Bit 0 DDRD0 0
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Figure 17-14. Data Direction Register D (DDRD) DDRD7-DDRD0 -- Data Direction Register D Bits These read/write bits control port D data direction. Reset clears DDRD7-DDRD0, configuring all port D pins as inputs. 1 = Corresponding port D pin configured as output 0 = Corresponding port D pin configured as input NOTE: Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from 0 to 1. Figure 17-15 shows the port D I/O logic.
MC68HC908GZ8 MOTOROLA Input/Output (I/O) Ports
Data Sheet 211
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Input/Output (I/O) Ports
READ DDRD ($0007)
WRITE DDRD ($0007) RESET INTERNAL DATA BUS WRITE PTD ($0003) PTDx VDD PTDPUEx INTERNAL PULLUP DEVICE PTDx DDRDx
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READ PTD ($0003)
Figure 17-15. Port D I/O Circuit When bit DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When bit DDRDx is a logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 17-5 summarizes the operation of the port D pins. Table 17-5. Port D Pin Functions
PTDPUE Bit 1 0 X DDRD Bit 0 0 1 PTD Bit X(1) X X I/O Pin Mode Input, VDD(2) Input, Hi-Z(4) Output Accesses to DDRD Read/Write DDRD7-DDRD0 DDRD7-DDRD0 DDRD7-DDRD0 Read Pin Pin PTD7-PTD0 Accesses to PTD Write PTD7-PTD0(3) PTD7-PTD0(3) PTD7-PTD0
1. X = Don't care 2. I/O pin pulled up to VDD by internal pullup device. 3. Writing affects data register, but does not affect input. 4. Hi-Z = High imp[edance
Data Sheet 212 Input/Output (I/O) Ports
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Input/Output (I/O) Ports Port E
17.5.3 Port D Input Pullup Enable Register The port D input pullup enable register (PTDPUE) contains a software configurable pullup device for each of the eight port D pins. Each bit is individually configurable and requires that the data direction register, DDRD, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port bit's DDRD is configured for output mode.
Address: Read: $000F Bit 7 Write: Reset: PTDPUE7 0 6 PTDPUE6 0 5 PTDPUE5 0 4 PTDPUE4 0 3 PTDPUE3 0 2 PTDPUE2 0 1 PTDPUE1 0 Bit 0 PTDPUE0 0
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Figure 17-16. Port D Input Pullup Enable Register (PTDPUE) PTDPUE7-PTDPUE0 -- Port D Input Pullup Enable Bits These writable bits are software programmable to enable pullup devices on an input port bit. 1 = Corresponding port D pin configured to have internal pullup 0 = Corresponding port D pin has internal pullup disconnected
17.6 Port E
Port E is a 6-bit special-function port that shares two of its pins with the enhanced serial communications interface (ESCI) module. 17.6.1 Port E Data Register The port E data register contains a data latch for each of the six port E pins.
Address: Read: Write: Reset: Alternate Function: = Unimplemented $0008 Bit 7 0 6 0 5 PTE5 4 PTE4 3 PTE3 2 PTE2 1 PTE1 Bit 0 PTE0
Unaffected by reset RxD TxD
Figure 17-17. Port E Data Register (PTE) PTE5-PTE0 -- Port E Data Bits These read/write bits are software-programmable. Data direction of each port E pin is under the control of the corresponding bit in data direction register E. Reset has no effect on port E data.
MC68HC908GZ8 MOTOROLA Input/Output (I/O) Ports Data Sheet 213
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Input/Output (I/O) Ports
NOTE: Data direction register E (DDRE) does not affect the data direction of port E pins that are being used by the ESCI module. However, the DDRE bits always determine whether reading port E returns the states of the latches or the states of the pins. See Table 17-6. RxD -- SCI Receive Data Input The PTE1/RxD pin is the receive data input for the ESCI module. When the enable SCI bit, ENSCI, is clear, the ESCI module is disabled, and the PTE1/RxD pin is available for general-purpose I/O. See Section 19. Enhanced Serial Communications Interface (ESCI) Module. TxD -- SCI Transmit Data Output The PTE0/TxD pin is the transmit data output for the ESCI module. When the enable SCI bit, ENSCI, is clear, the ESCI module is disabled, and the PTE0/TxD pin is available for general-purpose I/O. See Section 19. Enhanced Serial Communications Interface (ESCI) Module. 17.6.2 Data Direction Register E Data direction register E (DDRE) determines whether each port E pin is an input or an output. Writing a logic 1 to a DDRE bit enables the output buffer for the corresponding port E pin; a logic 0 disables the output buffer.
Address: Read: Write: Reset: 0 0 = Unimplemented $000C Bit 7 0 6 0 5 DDRE5 0 4 DDRE4 0 3 DDRE3 0 2 DDRE2 0 1 DDRE1 0 Bit 0 DDRE0 0
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Figure 17-18. Data Direction Register E (DDRE) DDRE5-DDRE0 -- Data Direction Register E Bits These read/write bits control port E data direction. Reset clears DDRE5-DDRE0, configuring all port E pins as inputs. 1 = Corresponding port E pin configured as output 0 = Corresponding port E pin configured as input NOTE: Avoid glitches on port E pins by writing to the port E data register before changing data direction register E bits from 0 to 1. Figure 17-19 shows the port E I/O logic.
Data Sheet 214 Input/Output (I/O) Ports
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Input/Output (I/O) Ports Port E
READ DDRE ($000C)
WRITE DDRE ($000C) INTERNAL DATA BUS RESET WRITE PTE ($0008) PTEx PTEx DDREx
READ PTE ($0008)
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Figure 17-19. Port E I/O Circuit When bit DDREx is a logic 1, reading address $0008 reads the PTEx data latch. When bit DDREx is a logic 0, reading address $0008 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 17-6 summarizes the operation of the port E pins. Table 17-6. Port E Pin Functions
DDRE Bit 0 1 PTE Bit X(1) X I/O Pin Mode Input, Hi-Z(2) Output Accesses to DDRE Read/Write DDRE5-DDRE0 DDRE5-DDRE0 Read Pin PTE5-PTE0 Accesses to PTE Write PTE5-PTE0(3) PTE5-PTE0
1. X = Don't care 2. Hi-Z = High impedance 3. Writing affects data register, but does not affect input.
MC68HC908GZ8 MOTOROLA Input/Output (I/O) Ports
Data Sheet 215
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Input/Output (I/O) Ports
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Data Sheet 216 Input/Output (I/O) Ports
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Data Sheet -- MC68HC908GZ8
Section 18. Random-Access Memory (RAM)
18.1 Introduction
This section describes the 1024 bytes of RAM (random-access memory).
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18.2 Functional Description
Addresses $0040 through $043F are RAM locations. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space. NOTE: For correct operation, the stack pointer must point only to RAM locations. Within page zero are 192 bytes of RAM. Because the location of the stack RAM is programmable, all page zero RAM locations can be used for I/O control and user data or code. When the stack pointer is moved from its reset location at $00FF out of page zero, direct addressing mode instructions can efficiently access all page zero RAM locations. Page zero RAM, therefore, provides ideal locations for frequently accessed global variables. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers. NOTE: For M6805 compatibility, the H register is not stacked. During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation.
MC68HC908GZ8 MOTOROLA Random-Access Memory (RAM)
Data Sheet 217
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Random-Access Memory (RAM)
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Data Sheet 218 Random-Access Memory (RAM)
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Data Sheet -- MC68HC908GZ8
Section 19. Enhanced Serial Communications Interface (ESCI) Module
19.1 Introduction
The enhanced serial communications interface (ESCI) module allows asynchronous communications with peripheral devices and other microcontroller units (MCU).
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19.2 Features
Features include: * * * * * * Full-duplex operation Standard mark/space non-return-to-zero (NRZ) format Programmable baud rates Programmable 8-bit or 9-bit character length Fine adjust baud rate prescalers for precise control of baud rate Arbiter module: - Measurement of received bit timings for baud rate recovery without use of external timer - Bitwise arbitration for arbitrated UART communications LIN specific enhanced features: - Generation of LIN 1.2 break symbols without extra software steps on each message - Break detection filtering to prevent false interrupts Separately enabled transmitter and receiver Separate receiver and transmitter central processor unit (CPU) interrupt requests Programmable transmitter output polarity Two receiver wakeup methods: - Idle line wakeup - address mark wakeup
*
* * * *
MC68HC908GZ8 MOTOROLA Enhanced Serial Communications Interface (ESCI) Module
Data Sheet 219
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Enhanced Serial Communications Interface (ESCI) Module
* Interrupt-driven operation with eight interrupt flags: - Transmitter empty - Transmission complete - Receiver full - Idle receiver input - Receiver overrun - Noise error - Framing error - Parity error Receiver framing error detection Hardware parity checking 1/16 bit-time noise detection
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* * *
19.3 Pin Name Conventions
The generic names of the ESCI input/output (I/O) pins are: * * RxD (receive data) TxD (transmit data)
ESCI I/O lines are implemented by sharing parallel I/O port pins. The full name of an ESCI input or output reflects the name of the shared port pin. Table 19-1 shows the full names and the generic names of the ESCI I/O pins. The generic pin names appear in the text of this section. Table 19-1. Pin Name Conventions
Generic Pin Names Full Pin Names RxD PTE1/RxD TxD PTE0/TxD
19.4 Functional Description
Figure 19-1 shows the structure of the ESCI module. The ESCI allows full-duplex, asynchronous, NRZ serial communication between the MCU and remote devices, including other MCUs. The transmitter and receiver of the ESCI operate independently, although they use the same baud rate generator. During normal operation, the CPU monitors the status of the ESCI, writes the data to be transmitted, and processes received data. For reference, a summary of the ESCI module input/output registers is provided in Figure 19-2.
Data Sheet 220 Enhanced Serial Communications Interface (ESCI) Module
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Enhanced Serial Communications Interface (ESCI) Module Functional Description
INTERNAL BUS
TRANSMITTER INTERRUPT CONTROL
ESCI DATA REGISTER RECEIVE SHIFT REGISTER LINR SCTIE TCIE SCRIE ILIE TE RE RWU SBK SCTE TC SCRF IDLE
ESCI DATA REGISTER RECEIVER INTERRUPT CONTROL ERROR INTERRUPT CONTROL TRANSMIT SHIFT REGISTER TXINV R8 T8
RxD ARBITERSCI_TxD TxD
RxD
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OR NF FE PE LOOPS LOOPS ENSCI FLAG CONTROL BKF RPF BAUD RATE GENERATOR M WAKE ILTY PEN PTY DATA SELECTION CONTROL
ORIE NEIE FEIE PEIE
WAKEUP CONTROL
RECEIVE CONTROL
TRANSMIT CONTROL
ENSCI
LINT
PRESCALER BUS CLOCK
/4
PRESCALER
/ 16
Figure 19-1. ESCI Module Block Diagram
MC68HC908GZ8 MOTOROLA Enhanced Serial Communications Interface (ESCI) Module
Data Sheet 221
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Enhanced Serial Communications Interface (ESCI) Module
Addr.
Register Name Read: ESCI Prescaler Register (SCPSC) Write: See page 246. Reset: Read: ESCI Arbiter Control Register (SCIACTL) Write: See page 250. Reset: Read: ESCI Arbiter Data Register (SCIADAT) Write: See page 251. Reset: Read: ESCI Control Register 1 (SCC1) Write: See page 235. Reset: Read: ESCI Control Register 2 (SCC2) Write: See page 237. Reset: Read: ESCI Control Register 3 (SCC3) Write: See page 239. Reset: Read: ESCI Status Register 1 (SCS1) Write: See page 241. Reset: Read: ESCI Status Register 2 (SCS2) Write: See page 243. Reset: Read: ESCI Data Register (SCDR) Write: See page 244. Reset: Read: ESCI Baud Rate Register (SCBR) Write: See page 244. Reset:
Bit 7 PDS2 0 AM1 0 ARD7
6 PDS1 0 ALOST
5 PDS0 0 AM0
4 PSSB4 0 ACLK 0 ARD4
3 PSSB3 0 AFIN
2 PSSB2 0 ARUN
1 PSSB1 0 AROVFL
Bit 0 PSSB0 0 ARD8
$0009
$000A
0 ARD6
0 ARD5
0 ARD3
0 ARD2
0 ARD1
0 ARD0
$000B
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0 LOOPS 0 SCTIE 0 R8
0 ENSCI 0 TCIE 0 T8
0 TXINV 0 SCRIE 0 R 0 SCRF
0 M 0 ILIE 0 R 0 IDLE
0 WAKE 0 TE 0 ORIE 0 OR
0 ILTY 0 RE 0 NEIE 0 NF
0 PEN 0 RWU 0 FEIE 0 FE
0 PTY 0 SBK 0 PEIE 0 PE
$0013
$0014
$0015
U SCTE
0 TC
$0016
1 0
1 0
0 0
0 0
0 0
0 0
0 BKF
0 RPF
$0017
0 R7 T7
0 R6 T6
0 R5 T5
0 R4 T4
0 R3 T3
0 R2 T2
0 R1 T1
0 R0 T0
$0018
Unaffected by reset LINT 0 LINR 0 = Unimplemented SCP1 0 SCP0 0 R R 0 = Reserved SCR2 0 SCR1 0 SCR0 0
$0019
Figure 19-2. ESCI I/O Register Summary
Data Sheet 222 Enhanced Serial Communications Interface (ESCI) Module
MC68HC908GZ8 MOTOROLA
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Enhanced Serial Communications Interface (ESCI) Module Functional Description
19.4.1 Data Format The SCI uses the standard non-return-to-zero mark/space data format illustrated in Figure 19-3.
PARITY OR DATA BIT BIT 7 STOP BIT PARITY OR DATA BIT BIT 6 BIT 7 BIT 8
START BIT
8-BIT DATA FORMAT (BIT M IN SCC1 CLEAR) BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6
NEXT START BIT
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START BIT
9-BIT DATA FORMAT (BIT M IN SCC1 SET) BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5
NEXT START BIT STOP BIT
Figure 19-3. SCI Data Formats 19.4.2 Transmitter Figure 19-4 shows the structure of the SCI transmitter and the registers are summarized in Figure 19-2. 19.4.2.1 Character Length The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in ESCI control register 1 (SCC1) determines character length. When transmitting 9-bit data, bit T8 in ESCI control register 3 (SCC3) is the ninth bit (bit 8). 19.4.2.2 Character Transmission During an ESCI transmission, the transmit shift register shifts a character out to the TxD pin. The ESCI data register (SCDR) is the write-only buffer between the internal data bus and the transmit shift register.
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INTERNAL BUS
/4
SCP1 SCP0 SCR1 SCR2 SCR0 TRANSMITTER CPU INTERRUPT REQUEST
PRESCALER
BAUD DIVIDER
/ 16
ESCI DATA REGISTER
H
8
7
6
5
4
3
2
1
0
START L
STOP
11-BIT TRANSMIT SHIFT REGISTER
SCI_TxD
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TXINV
PRESCALER
M PEN PTY PARITY GENERATION LOAD FROM SCDR
BUS CLOCK
SHIFT ENABLE
PDS1 PDS0 PSSB4 PSSB3 PSSB2 PSSB1 PSSB0
T8
TRANSMITTER CONTROL LOGIC
SCTE SCTE SCTIE TC TCIE
PREAMBLE (ALL ONES)
LOOPS SCTIE TC TCIE ENSCI TE LINT
Figure 19-4. ESCI Transmitter To initiate an ESCI transmission: 1. Enable the ESCI by writing a logic 1 to the enable ESCI bit (ENSCI) in ESCI control register 1 (SCC1). 2. Enable the transmitter by writing a logic 1 to the transmitter enable bit (TE) in ESCI control register 2 (SCC2). 3. Clear the ESCI transmitter empty bit (SCTE) by first reading ESCI status register 1 (SCS1) and then writing to the SCDR. For 9-bit data, also write the T8 bit in SCC3. 4. Repeat step 3 for each subsequent transmission. At the start of a transmission, transmitter control logic automatically loads the transmit shift register with a preamble of logic 1s. After the preamble shifts out, control logic transfers the SCDR data into the transmit shift register. A logic 0 start
Data Sheet 224 Enhanced Serial Communications Interface (ESCI) Module
BREAK (ALL ZEROS) SBK
PDS2
MSB
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bit automatically goes into the least significant bit (LSB) position of the transmit shift register. A logic 1 stop bit goes into the most significant bit (MSB) position. The ESCI transmitter empty bit, SCTE, in SCS1 becomes set when the SCDR transfers a byte to the transmit shift register. The SCTE bit indicates that the SCDR can accept new data from the internal data bus. If the ESCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the SCTE bit generates a transmitter CPU interrupt request. When the transmit shift register is not transmitting a character, the TxD pin goes to the idle condition, logic 1. If at any time software clears the ENSCI bit in ESCI control register 1 (SCC1), the transmitter and receiver relinquish control of the port E pins. 19.4.2.3 Break Characters Writing a logic 1 to the send break bit, SBK, in SCC2 loads the transmit shift register with a break character. For TXINV = 0 (output not inverted), a transmitted break character contains all logic 0s and has no start, stop, or parity bit. Break character length depends on the M bit in SCC1 and the LINR bits in SCBR. As long as SBK is at logic 1, transmitter logic continuously loads break characters into the transmit shift register. After software clears the SBK bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. The automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next character. When LINR is cleared in SCBR, the ESCI recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit should be, resulting in a total of 10 or 11 consecutive logic 0 data bits. When LINR is set in SCBR, the ESCI recognizes a break character when a start bit is followed by 9 or 10 logic 0 data bits and a logic 0 where the stop bit should be, resulting in a total of 11 or 12 consecutive logic 0 data bits. Receiving a break character has these effects on ESCI registers: * * * * * * Sets the framing error bit (FE) in SCS1 Sets the ESCI receiver full bit (SCRF) in SCS1 Clears the ESCI data register (SCDR) Clears the R8 bit in SCC3 Sets the break flag bit (BKF) in SCS2 May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits
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19.4.2.4 Idle Characters For TXINV = 0 (output not inverted), a transmitted idle character contains all logic 1s and has no start, stop, or parity bit. Idle character length depends on the M bit in SCC1. The preamble is a synchronizing idle character that begins every transmission. If the TE bit is cleared during a transmission, the TxD pin becomes idle after completion of the transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle character to be sent after the character currently being transmitted.
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NOTE:
When queueing an idle character, return the TE bit to logic 1 before the stop bit of the current character shifts out to the TxD pin. Setting TE after the stop bit appears on TxD causes data previously written to the SCDR to be lost. A good time to toggle the TE bit for a queued idle character is when the SCTE bit becomes set and just before writing the next byte to the SCDR.
19.4.2.5 Inversion of Transmitted Output The transmit inversion bit (TXINV) in ESCI control register 1 (SCC1) reverses the polarity of transmitted data. All transmitted values including idle, break, start, and stop bits, are inverted when TXINV is at logic 1. See 19.8.1 ESCI Control Register 1. 19.4.2.6 Transmitter Interrupts These conditions can generate CPU interrupt requests from the ESCI transmitter: * ESCI transmitter empty (SCTE) -- The SCTE bit in SCS1 indicates that the SCDR has transferred a character to the transmit shift register. SCTE can generate a transmitter CPU interrupt request. Setting the ESCI transmit interrupt enable bit, SCTIE, in SCC2 enables the SCTE bit to generate transmitter CPU interrupt requests. Transmission complete (TC) -- The TC bit in SCS1 indicates that the transmit shift register and the SCDR are empty and that no break or idle character has been generated. The transmission complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to generate transmitter CPU interrupt requests.
*
19.4.3 Receiver Figure 19-5 shows the structure of the ESCI receiver. The receiver I/O registers are summarized in Figure 19-2.
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INTERNAL BUS
LINR SCP1 SCP0
SCR1 SCR2 SCR0 START 0 L RWU PRESCALER BAUD DIVIDER ESCI DATA REGISTER
STOP
/4
PRESCALER
/ 16
DATA RECOVERY
11-BIT RECEIVE SHIFT REGISTER 8 7 6 5 4 3 2 1
RxD
H ALL ONES
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BUS CLOCK
BKF PDS2 PDS1 PDS0 PSSB4 PSSB3 PSSB2 PSSB1 PSSB0 M WAKE ILTY PEN PTY RPF
ALL ZEROS
MSB
SCRF WAKEUP LOGIC PARITY CHECKING IDLE
R8
CPU INTERRUPT REQUEST
IDLE ILIE SCRF SCRIE
ILIE
SCRIE
OR ORIE ERROR CPU INTERRUPT REQUEST NF NEIE FE FEIE PE PEIE
OR ORIE NF NEIE FE FEIE PE PEIE
Figure 19-5. ESCI Receiver Block Diagram
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19.4.3.1 Character Length The receiver can accommodate either 8-bit or 9-bit data. The state of the M bit in ESCI control register 1 (SCC1) determines character length. When receiving 9-bit data, bit R8 in ESCI control register 3 (SCC3) is the ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth bit (bit 7). 19.4.3.2 Character Reception During an ESCI reception, the receive shift register shifts characters in from the RxD pin. The ESCI data register (SCDR) is the read-only buffer between the internal data bus and the receive shift register.
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After a complete character shifts into the receive shift register, the data portion of the character transfers to the SCDR. The ESCI receiver full bit, SCRF, in ESCI status register 1 (SCS1) becomes set, indicating that the received byte can be read. If the ESCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the SCRF bit generates a receiver CPU interrupt request. 19.4.3.3 Data Sampling The receiver samples the RxD pin at the RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock is resynchronized at these times (see Figure 19-6): * After every start bit * After the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at RT8, RT9, and RT10 returns a valid logic 1 and the majority of the next RT8, RT9, and RT10 samples returns a valid logic 0) To locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.
START BIT LSB
RxD
SAMPLES
START BIT QUALIFICATION
START BIT DATA VERIFICATION SAMPLING
RT CLOCK RT CLOCK STATE RT CLOCK RESET RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT2 RT3 RT4
Figure 19-6. Receiver Data Sampling
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To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Table 19-2 summarizes the results of the start bit verification samples. Table 19-2. Start Bit Verification
RT3, RT5, and RT7 Samples 000 001 010 011 100 101 110 111 Start Bit Verification Yes Yes Yes No Yes No No No Noise Flag 0 1 1 0 1 0 0 0
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If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins. To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 19-3 summarizes the results of the data bit samples. Table 19-3. Data Bit Recovery
RT8, RT9, and RT10 Samples 000 001 010 011 100 101 110 111 Data Bit Determination 0 0 0 1 0 1 1 1 Noise Flag 0 1 1 1 1 1 1 0
NOTE:
The RT8, RT9, and RT10 samples do not affect start bit verification. If any or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a successful start bit verification, the noise flag (NF) is set and the receiver assumes that the bit is a start bit. To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 19-4 summarizes the results of the stop bit samples.
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Table 19-4. Stop Bit Recovery
RT8, RT9, and RT10 Samples 000 001 010 011 100 101 110 111 Framing Error Flag 1 1 1 0 1 0 0 0 Noise Flag 0 1 1 1 1 1 1 0
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19.4.3.4 Framing Errors If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character, it sets the framing error bit, FE, in SCS1. A break character also sets the FE bit because a break character has no stop bit. The FE bit is set at the same time that the SCRF bit is set. 19.4.3.5 Baud Rate Tolerance A transmitting device may be operating at a baud rate below or above the receiver baud rate. Accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the actual stop bit. Then a noise error occurs. If more than one of the samples is outside the stop bit, a framing error occurs. In most applications, the baud rate tolerance is much more than the degree of misalignment that is likely to occur. As the receiver samples an incoming character, it resynchronizes the RT clock on any valid falling edge within the character. Resynchronization within characters corrects misalignments between transmitter bit times and receiver bit times. Slow Data Tolerance Figure 19-7 shows how much a slow received character can be misaligned without causing a noise error or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data samples at RT8, RT9, and RT10.
MSB
STOP
RECEIVER RT CLOCK RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9
DATA SAMPLES
Figure 19-7. Slow Data
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For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times x 16 RT cycles + 10 RT cycles = 154 RT cycles. With the misaligned character shown in Figure 19-7, the receiver counts 154 RT cycles at the point when the count of the transmitting device is 9 bit times x 16 RT cycles + 3 RT cycles = 147 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit character with no errors is: 154 - 147 x 100 = 4.54% ------------------------154
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For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times x 16 RT cycles + 10 RT cycles = 170 RT cycles. With the misaligned character shown in Figure 19-7, the receiver counts 170 RT cycles at the point when the count of the transmitting device is 10 bit times x 16 RT cycles + 3 RT cycles = 163 RT cycles. The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is: 170 - 163 x 100 = 4.12% ------------------------170 Fast Data Tolerance Figure 19-8 shows how much a fast received character can be misaligned without causing a noise error or a framing error. The fast stop bit ends at RT10 instead of RT16 but is still there for the stop bit data samples at RT8, RT9, and RT10.
STOP
IDLE OR NEXT CHARACTER
RECEIVER RT CLOCK RT10 RT11 RT12 RT13 RT14 RT15 RT16 RT1 RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9
DATA SAMPLES
Figure 19-8. Fast Data For an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times x 16 RT cycles + 10 RT cycles = 154 RT cycles. With the misaligned character shown in Figure 19-8, the receiver counts 154 RT cycles at the point when the count of the transmitting device is 10 bit times x 16 RT cycles = 160 RT cycles.
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The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is 154 - 160 x 100 = 3.90%. ------------------------154 For a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times x 16 RT cycles + 10 RT cycles = 170 RT cycles. With the misaligned character shown in Figure 19-8, the receiver counts 170 RT cycles at the point when the count of the transmitting device is 11 bit times x 16 RT cycles = 176 RT cycles.
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The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is: 170 - 176 x 100 = 3.53%. ------------------------170 19.4.3.6 Receiver Wakeup So that the MCU can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. Setting the receiver wakeup bit, RWU, in SCC2 puts the receiver into a standby state during which receiver interrupts are disabled. Depending on the state of the WAKE bit in SCC1, either of two conditions on the RxD pin can bring the receiver out of the standby state: 1. Address mark -- An address mark is a logic 1 in the MSB position of a received character. When the WAKE bit is set, an address mark wakes the receiver from the standby state by clearing the RWU bit. The address mark also sets the ESCI receiver full bit, SCRF. Software can then compare the character containing the address mark to the user-defined address of the receiver. If they are the same, the receiver remains awake and processes the characters that follow. If they are not the same, software can set the RWU bit and put the receiver back into the standby state. 2. Idle input line condition -- When the WAKE bit is clear, an idle character on the RxD pin wakes the receiver from the standby state by clearing the RWU bit. The idle character that wakes the receiver does not set the receiver idle bit, IDLE, or the ESCI receiver full bit, SCRF. The idle line type bit, ILTY, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. NOTE: With the WAKE bit clear, setting the RWU bit after the RxD pin has been idle will cause the receiver to wakeup.
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19.4.3.7 Receiver Interrupts These sources can generate CPU interrupt requests from the ESCI receiver: * ESCI receiver full (SCRF) -- The SCRF bit in SCS1 indicates that the receive shift register has transferred a character to the SCDR. SCRF can generate a receiver CPU interrupt request. Setting the ESCI receive interrupt enable bit, SCRIE, in SCC2 enables the SCRF bit to generate receiver CPU interrupts. Idle input (IDLE) -- The IDLE bit in SCS1 indicates that 10 or 11 consecutive logic 1s shifted in from the RxD pin. The idle line interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to generate CPU interrupt requests.
*
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19.4.3.8 Error Interrupts These receiver error flags in SCS1 can generate CPU interrupt requests: * Receiver overrun (OR) -- The OR bit indicates that the receive shift register shifted in a new character before the previous character was read from the SCDR. The previous character remains in the SCDR, and the new character is lost. The overrun interrupt enable bit, ORIE, in SCC3 enables OR to generate ESCI error CPU interrupt requests. Noise flag (NF) -- The NF bit is set when the ESCI detects noise on incoming data or break characters, including start, data, and stop bits. The noise error interrupt enable bit, NEIE, in SCC3 enables NF to generate ESCI error CPU interrupt requests. Framing error (FE) -- The FE bit in SCS1 is set when a logic 0 occurs where the receiver expects a stop bit. The framing error interrupt enable bit, FEIE, in SCC3 enables FE to generate ESCI error CPU interrupt requests. Parity error (PE) -- The PE bit in SCS1 is set when the ESCI detects a parity error in incoming data. The parity error interrupt enable bit, PEIE, in SCC3 enables PE to generate ESCI error CPU interrupt requests.
*
*
*
19.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 19.5.1 Wait Mode The ESCI module remains active in wait mode. Any enabled CPU interrupt request from the ESCI module can bring the MCU out of wait mode. If ESCI module functions are not required during wait mode, reduce power consumption by disabling the module before executing the WAIT instruction.
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19.5.2 Stop Mode The ESCI module is inactive in stop mode. The STOP instruction does not affect ESCI register states. ESCI module operation resumes after the MCU exits stop mode. Because the internal clock is inactive during stop mode, entering stop mode during an ESCI transmission or reception results in invalid data.
19.6 ESCI During Break Module Interrupts
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The BCFE bit in the break flag control register (SBFCR) enables software to clear status bits during the break state. See Section 6. Break Module (BRK). To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit.
19.7 I/O Signals
Port E shares two of its pins with the ESCI module. The two ESCI I/O pins are: * * PTE0/TxD -- transmit data PTE1/RxD -- receive data
19.7.1 PTE0/TxD (Transmit Data) The PTE0/TxD pin is the serial data output from the ESCI transmitter. The ESCI shares the PTE0/TxD pin with port E. When the ESCI is enabled, the PTE0/TxD pin is an output regardless of the state of the DDRE0 bit in data direction register E (DDRE). 19.7.2 PTE1/RxD (Receive Data) The PTE1/RxD pin is the serial data input to the ESCI receiver. The ESCI shares the PTE1/RxD pin with port E. When the ESCI is enabled, the PTE1/RxD pin is an input regardless of the state of the DDRE1 bit in data direction register E (DDRE).
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19.8 I/O Registers
These I/O registers control and monitor ESCI operation: * * * * * * * ESCI control register 1, SCC1 ESCI control register 2, SCC2 ESCI control register 3, SCC3 ESCI status register 1, SCS1 ESCI status register 2, SCS2 ESCI data register, SCDR ESCI baud rate register, SCBR ESCI prescaler register, SCPSC ESCI arbiter control register, SCIACTL ESCI arbiter data register, SCIADAT
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* * *
19.8.1 ESCI Control Register 1 ESCI control register 1 (SCC1): * * * * * * * * Enables loop mode operation Enables the ESCI Controls output polarity Controls character length Controls ESCI wakeup method Controls idle character detection Enables parity function Controls parity type
:
Address: $0013 Bit 7 Read: Write: Reset: LOOPS 0 6 ENSCI 0 5 TXINV 0 4 M 0 3 WAKE 0 2 ILTY 0 1 PEN 0 Bit 0 PTY 0
Figure 19-9. ESCI Control Register 1 (SCC1) LOOPS -- Loop Mode Select Bit This read/write bit enables loop mode operation. In loop mode the RxD pin is disconnected from the ESCI, and the transmitter output goes into the receiver input. Both the transmitter and the receiver must be enabled to use loop mode. Reset clears the LOOPS bit. 1 = Loop mode enabled 0 = Normal operation enabled
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ENSCI -- Enable ESCI Bit This read/write bit enables the ESCI and the ESCI baud rate generator. Clearing ENSCI sets the SCTE and TC bits in ESCI status register 1 and disables transmitter interrupts. Reset clears the ENSCI bit. 1 = ESCI enabled 0 = ESCI disabled TXINV -- Transmit Inversion Bit This read/write bit reverses the polarity of transmitted data. Reset clears the TXINV bit. 1 = Transmitter output inverted 0 = Transmitter output not inverted
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NOTE:
Setting the TXINV bit inverts all transmitted values including idle, break, start, and stop bits. M -- Mode (Character Length) Bit This read/write bit determines whether ESCI characters are eight or nine bits long (See Table 19-5).The ninth bit can serve as a receiver wakeup signal or as a parity bit. Reset clears the M bit. 1 = 9-bit ESCI characters 0 = 8-bit ESCI characters Table 19-5. Character Format Selection
Control Bits M 0 1 0 0 1 1 PEN:PTY 0X 0X 10 11 10 11 Start Bits 1 1 1 1 1 1 Data Bits 8 9 7 7 8 8 Character Format Parity None None Even Odd Even Odd Stop Bits 1 1 1 1 1 1 Character Length 10 bits 11 bits 10 bits 10 bits 11 bits 11 bits
WAKE -- Wakeup Condition Bit This read/write bit determines which condition wakes up the ESCI: a logic 1 (address mark) in the MSB position of a received character or an idle condition on the RxD pin. Reset clears the WAKE bit. 1 = Address mark wakeup 0 = Idle line wakeup ILTY -- Idle Line Type Bit This read/write bit determines when the ESCI starts counting logic 1s as idle character bits. The counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding the stop
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bit may cause false recognition of an idle character. Beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. Reset clears the ILTY bit. 1 = Idle character bit count begins after stop bit 0 = Idle character bit count begins after start bit PEN -- Parity Enable Bit This read/write bit enables the ESCI parity function (see Table 19-5). When enabled, the parity function inserts a parity bit in the MSB position (see Table 19-3). Reset clears the PEN bit. 1 = Parity function enabled 0 = Parity function disabled
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PTY -- Parity Bit This read/write bit determines whether the ESCI generates and checks for odd parity or even parity (see Table 19-5). Reset clears the PTY bit. 1 = Odd parity 0 = Even parity NOTE: Changing the PTY bit in the middle of a transmission or reception can generate a parity error.
19.8.2 ESCI Control Register 2 ESCI control register 2 (SCC2): * Enables these CPU interrupt requests: - SCTE bit to generate transmitter CPU interrupt requests - TC bit to generate transmitter CPU interrupt requests - SCRF bit to generate receiver CPU interrupt requests - IDLE bit to generate receiver CPU interrupt requests Enables the transmitter Enables the receiver Enables ESCI wakeup Transmits ESCI break characters
* * * *
Address: $0014 Bit 7 Read: Write: Reset: SCTIE 0 6 TCIE 0 5 SCRIE 0 4 ILIE 0 3 TE 0 2 RE 0 1 RWU 0 Bit 0 SBK 0
Figure 19-10. ESCI Control Register 2 (SCC2)
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SCTIE -- ESCI Transmit Interrupt Enable Bit This read/write bit enables the SCTE bit to generate ESCI transmitter CPU interrupt requests. Setting the SCTIE bit in SCC2 enables the SCTE bit to generate CPU interrupt requests. Reset clears the SCTIE bit. 1 = SCTE enabled to generate CPU interrupt 0 = SCTE not enabled to generate CPU interrupt TCIE -- Transmission Complete Interrupt Enable Bit This read/write bit enables the TC bit to generate ESCI transmitter CPU interrupt requests. Reset clears the TCIE bit. 1 = TC enabled to generate CPU interrupt requests 0 = TC not enabled to generate CPU interrupt requests
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SCRIE -- ESCI Receive Interrupt Enable Bit This read/write bit enables the SCRF bit to generate ESCI receiver CPU interrupt requests. Setting the SCRIE bit in SCC2 enables the SCRF bit to generate CPU interrupt requests. Reset clears the SCRIE bit. 1 = SCRF enabled to generate CPU interrupt 0 = SCRF not enabled to generate CPU interrupt ILIE -- Idle Line Interrupt Enable Bit This read/write bit enables the IDLE bit to generate ESCI receiver CPU interrupt requests. Reset clears the ILIE bit. 1 = IDLE enabled to generate CPU interrupt requests 0 = IDLE not enabled to generate CPU interrupt requests TE -- Transmitter Enable Bit Setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the TxD pin. If software clears the TE bit, the transmitter completes any transmission in progress before the TxD returns to the idle condition (logic 1). Clearing and then setting TE during a transmission queues an idle character to be sent after the character currently being transmitted. Reset clears the TE bit. 1 = Transmitter enabled 0 = Transmitter disabled NOTE: Writing to the TE bit is not allowed when the enable ESCI bit (ENSCI) is clear. ENSCI is in ESCI control register 1. RE -- Receiver Enable Bit Setting this read/write bit enables the receiver. Clearing the RE bit disables the receiver but does not affect receiver interrupt flag bits. Reset clears the RE bit. 1 = Receiver enabled 0 = Receiver disabled NOTE: Writing to the RE bit is not allowed when the enable ESCI bit (ENSCI) is clear. ENSCI is in ESCI control register 1.
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Enhanced Serial Communications Interface (ESCI) Module I/O Registers
RWU -- Receiver Wakeup Bit This read/write bit puts the receiver in a standby state during which receiver interrupts are disabled. The WAKE bit in SCC1 determines whether an idle input or an address mark brings the receiver out of the standby state and clears the RWU bit. Reset clears the RWU bit. 1 = Standby state 0 = Normal operation SBK -- Send Break Bit Setting and then clearing this read/write bit transmits a break character followed by a logic 1. The logic 1 after the break character guarantees recognition of a valid start bit. If SBK remains set, the transmitter continuously transmits break characters with no logic 1s between them. Reset clears the SBK bit. 1 = Transmit break characters 0 = No break characters being transmitted NOTE: Do not toggle the SBK bit immediately after setting the SCTE bit. Toggling SBK before the preamble begins causes the ESCI to send a break character instead of a preamble.
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19.8.3 ESCI Control Register 3 ESCI control register 3 (SCC3): * * Stores the ninth ESCI data bit received and the ninth ESCI data bit to be transmitted. Enables these interrupts: - Receiver overrun - Noise error - Framing error - Parity error
$0015 Bit 7 Read: Write: Reset: U R8 6 T8 0 5 R 0 4 R 0 R 3 ORIE 0 = Reserved 2 NEIE 0 1 FEIE 0 Bit 0 PEIE 0
Address:
= Unimplemented
U = Unaffected
Figure 19-11. ESCI Control Register 3 (SCC3) R8 -- Received Bit 8 When the ESCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received character. R8 is received at the same time that the SCDR receives the other 8 bits.
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When the ESCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect on the R8 bit. T8 -- Transmitted Bit 8 When the ESCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8) of the transmitted character. T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into the transmit shift register. Reset clears the T8 bit. ORIE -- Receiver Overrun Interrupt Enable Bit This read/write bit enables ESCI error CPU interrupt requests generated by the receiver overrun bit, OR. Reset clears ORIE. 1 = ESCI error CPU interrupt requests from OR bit enabled 0 = ESCI error CPU interrupt requests from OR bit disabled NEIE -- Receiver Noise Error Interrupt Enable Bit This read/write bit enables ESCI error CPU interrupt requests generated by the noise error bit, NE. Reset clears NEIE. 1 = ESCI error CPU interrupt requests from NE bit enabled 0 = ESCI error CPU interrupt requests from NE bit disabled FEIE -- Receiver Framing Error Interrupt Enable Bit This read/write bit enables ESCI error CPU interrupt requests generated by the framing error bit, FE. Reset clears FEIE. 1 = ESCI error CPU interrupt requests from FE bit enabled 0 = ESCI error CPU interrupt requests from FE bit disabled PEIE -- Receiver Parity Error Interrupt Enable Bit This read/write bit enables ESCI receiver CPU interrupt requests generated by the parity error bit, PE. Reset clears PEIE. 1 = ESCI error CPU interrupt requests from PE bit enabled 0 = ESCI error CPU interrupt requests from PE bit disabled 19.8.4 ESCI Status Register 1 ESCI status register 1 (SCS1) contains flags to signal these conditions: * * * * * * * * Transfer of SCDR data to transmit shift register complete Transmission complete Transfer of receive shift register data to SCDR complete Receiver input idle Receiver overrun Noisy data Framing error Parity error
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Data Sheet 240 Enhanced Serial Communications Interface (ESCI) Module
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Enhanced Serial Communications Interface (ESCI) Module I/O Registers
Address: Read: Write: Reset:
$0016 Bit 7 SCTE 1 6 TC 1 5 SCRF 0 4 IDLE 0 3 OR 0 2 NF 0 1 FE 0 Bit 0 PE 0
= Unimplemented
Figure 19-12. ESCI Status Register 1 (SCS1) SCTE -- ESCI Transmitter Empty Bit This clearable, read-only bit is set when the SCDR transfers a character to the transmit shift register. SCTE can generate an ESCI transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set, SCTE generates an ESCI transmitter CPU interrupt request. In normal operation, clear the SCTE bit by reading SCS1 with SCTE set and then writing to SCDR. Reset sets the SCTE bit. 1 = SCDR data transferred to transmit shift register 0 = SCDR data not transferred to transmit shift register TC -- Transmission Complete Bit This read-only bit is set when the SCTE bit is set, and no data, preamble, or break character is being transmitted. TC generates an ESCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also set. TC is cleared automatically when data, preamble, or break is queued and ready to be sent. There may be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the transmission actually starting. Reset sets the TC bit. 1 = No transmission in progress 0 = Transmission in progress SCRF -- ESCI Receiver Full Bit This clearable, read-only bit is set when the data in the receive shift register transfers to the ESCI data register. SCRF can generate an ESCI receiver CPU interrupt request. When the SCRIE bit in SCC2 is set the SCRF generates a CPU interrupt request. In normal operation, clear the SCRF bit by reading SCS1 with SCRF set and then reading the SCDR. Reset clears SCRF. 1 = Received data available in SCDR 0 = Data not available in SCDR IDLE -- Receiver Idle Bit This clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input. IDLE generates an ESCI receiver CPU interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE bit by reading SCS1 with IDLE set and then reading the SCDR. After the receiver is enabled, it must receive a valid character that sets the SCRF bit before an idle condition can set the IDLE bit. Also, after the IDLE bit has been cleared, a valid character must again set the SCRF bit before an idle condition can set the IDLE bit. Reset clears the IDLE bit. 1 = Receiver input idle 0 = Receiver input active (or idle since the IDLE bit was cleared)
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OR -- Receiver Overrun Bit This clearable, read-only bit is set when software fails to read the SCDR before the receive shift register receives the next character. The OR bit generates an ESCI error CPU interrupt request if the ORIE bit in SCC3 is also set. The data in the shift register is lost, but the data already in the SCDR is not affected. Clear the OR bit by reading SCS1 with OR set and then reading the SCDR. Reset clears the OR bit. 1 = Receive shift register full and SCRF = 1 0 = No receiver overrun Software latency may allow an overrun to occur between reads of SCS1 and SCDR in the flag-clearing sequence. Figure 19-13 shows the normal flag-clearing sequence and an example of an overrun caused by a delayed flag-clearing sequence. The delayed read of SCDR does not clear the OR bit because OR was not set when SCS1 was read. Byte 2 caused the overrun and is lost. The next flag-clearing sequence reads byte 3 in the SCDR instead of byte 2. In applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flag-clearing routine can check the OR bit in a second read of SCS1 after reading the data register.
NORMAL FLAG CLEARING SEQUENCE SCRF = 1 SCRF = 0 SCRF = 1 SCRF = 0 SCRF = 1 SCRF = 0 BYTE 4 READ SCS1 SCRF = 1 OR = 0 READ SCDR BYTE 3 BYTE 4 READ SCS1 SCRF = 1 OR = 1 READ SCDR BYTE 3
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BYTE 1 READ SCS1 SCRF = 1 OR = 0 READ SCDR BYTE 1
BYTE 2 READ SCS1 SCRF = 1 OR = 0 READ SCDR BYTE 2
BYTE 3
DELAYED FLAG CLEARING SEQUENCE SCRF = 1 OR = 1 SCRF = 0 OR = 1 SCRF = 1 SCRF = 1 OR = 1 SCRF = 0 OR = 0
BYTE 1
BYTE 2 READ SCS1 SCRF = 1 OR = 0 READ SCDR BYTE 1
BYTE 3
Figure 19-13. Flag Clearing Sequence
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NF -- Receiver Noise Flag Bit This clearable, read-only bit is set when the ESCI detects noise on the RxD pin. NF generates an NF CPU interrupt request if the NEIE bit in SCC3 is also set. Clear the NF bit by reading SCS1 and then reading the SCDR. Reset clears the NF bit. 1 = Noise detected 0 = No noise detected FE -- Receiver Framing Error Bit This clearable, read-only bit is set when a logic 0 is accepted as the stop bit. FE generates an ESCI error CPU interrupt request if the FEIE bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set and then reading the SCDR. Reset clears the FE bit. 1 = Framing error detected 0 = No framing error detected PE -- Receiver Parity Error Bit This clearable, read-only bit is set when the ESCI detects a parity error in incoming data. PE generates a PE CPU interrupt request if the PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with PE set and then reading the SCDR. Reset clears the PE bit. 1 = Parity error detected 0 = No parity error detected 19.8.5 ESCI Status Register 2 ESCI status register 2 (SCS2) contains flags to signal these conditions: * * Break character detected Incoming data
$0017 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 = Unimplemented 0 6 0 5 0 4 0 3 0 2 0 1 BKF Bit 0 RPF
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Address:
Figure 19-14. ESCI Status Register 2 (SCS2) BKF -- Break Flag Bit This clearable, read-only bit is set when the ESCI detects a break character on the RxD pin. In SCS1, the FE and SCRF bits are also set. In 9-bit character transmissions, the R8 bit in SCC3 is cleared. BKF does not generate a CPU interrupt request. Clear BKF by reading SCS2 with BKF set and then reading the SCDR. Once cleared, BKF can become set again only after logic 1s again appear on the RxD pin followed by another break character. Reset clears the BKF bit. 1 = Break character detected 0 = No break character detected
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RPF -- Reception in Progress Flag Bit This read-only bit is set when the receiver detects a logic 0 during the RT1 time period of the start bit search. RPF does not generate an interrupt request. RPF is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch), or when the receiver detects an idle character. Polling RPF before disabling the ESCI module or entering stop mode can show whether a reception is in progress. 1 = Reception in progress 0 = No reception in progress 19.8.6 ESCI Data Register
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The ESCI data register (SCDR) is the buffer between the internal data bus and the receive and transmit shift registers. Reset has no effect on data in the ESCI data register.
Address: Read: Write: Reset: $0018 Bit 7 R7 T7 6 R6 T6 5 R5 T5 4 R4 T4 3 R3 T3 2 R2 T2 1 R1 T1 Bit 0 R0 T0
Unaffected by reset
Figure 19-15. ESCI Data Register (SCDR) R7/T7:R0/T0 -- Receive/Transmit Data Bits Reading address $0018 accesses the read-only received data bits, R7:R0. Writing to address $0018 writes the data to be transmitted, T7:T0. Reset has no effect on the ESCI data register. NOTE: Do not use read-modify-write instructions on the ESCI data register.
19.8.7 ESCI Baud Rate Register The ESCI baud rate register (SCBR) together with the ESCI prescaler register selects the baud rate for both the receiver and the transmitter. NOTE: There are two prescalers available to adjust the baud rate. One in the ESCI baud rate register and one in the ESCI prescaler register.
Address: Read: Write: Reset: $0019 Bit 7 LINT 0 6 LINR 0 5 SCP1 0 4 SCP0 0 R 3 R 0 = Reserved 2 SCR2 0 1 SCR1 0 Bit 0 SCR0 0
= Unimplemented
Figure 19-16. ESCI Baud Rate Register (SCBR)
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Enhanced Serial Communications Interface (ESCI) Module I/O Registers
LINT -- LIN Break Symbol Transmit Enable This read/write bit selects the enhanced ESCI features for master nodes in the local interconnect network (LIN) protocol (version 1.2) as shown in Table 19-6. Reset clears LINT. Table 19-6. ESCI LIN Master Node Control Bits
LINT 0 1 1 M X 0 1 Functionality Normal ESCI functionality 13-bit generation enabled for LIN transmitter 14-bit generation enabled for LIN transmitter
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NOTE:
LIN master nodes require significantly tighter timing tolerances than slave nodes. Be sure to consult the current LIN specification to ensure that timing requirements are met properly. Generally, these timing tolerances require crystals or oscillators to be used, rather than internal clocking circuits. LINR -- LIN Break Symbol Receiver Bits This read/write bit selects the enhanced ESCI features for slave nodes in the local interconnect network (LIN) protocol as shown in Table 19-7. Reset clears LINR. Table 19-7. ESCI LIN Slave Node Control Bits
LINR 0 1 1 M X 0 1 Functionality Normal ESCI functionality 11-bit break detect enabled for LIN receiver 12-bit break detect enabled for LIN receiver
In LIN (version 1.2) systems, the master node transmits a break character which will appear as 11.05-14.95 dominant bits to the slave node. A data character of 0x00 sent from the master might appear as 7.65-10.35 dominant bit times. This is due to the oscillator tolerance requirement that the slave node must be within 15% of the master node's oscillator. Since a slave node cannot know if it is running faster or slower than the master node (prior to synchronization), the LINR bit allows the slave node to differentiate between a 0x00 character of 10.35 bits and a break character of 11.05 bits. The break symbol length must be verified in software in any case, but the LINR bit serves as a filter, preventing false detections of break characters that are really 0x00 data characters.
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SCP1 and SCP0 -- ESCI Baud Rate Register Prescaler Bits These read/write bits select the baud rate register prescaler divisor as shown in Table 19-8. Reset clears SCP1 and SCP0. Table 19-8. ESCI Baud Rate Prescaling
SCP[1:0] 00 01 10 11 Baud Rate Register Prescaler Divisor (BPD) 1 3 4 13
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SCR2-SCR0 -- ESCI Baud Rate Select Bits These read/write bits select the ESCI baud rate divisor as shown in Table 19-9. Reset clears SCR2-SCR0. Table 19-9. ESCI Baud Rate Selection
SCR[2:1:0] 000 001 010 011 100 101 110 111 Baud Rate Divisor (BD) 1 2 4 8 16 32 64 128
19.8.8 ESCI Prescaler Register The ESCI prescaler register (SCPSC) together with the ESCI baud rate register selects the baud rate for both the receiver and the transmitter. NOTE: There are two prescalers available to adjust the baud rate. One in the ESCI baud rate register and one in the ESCI prescaler register.
Address: Read: Write: Reset: $0009 Bit 7 PDS2 0 6 PDS1 0 5 PDS0 0 4 PSSB4 0 3 PSSB3 0 2 PSSB2 0 1 PSSB1 0 Bit 0 PSSB0 0
Figure 19-17. ESCI Prescaler Register (SCPSC)
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PDS2-PDS0 -- Prescaler Divisor Select Bits These read/write bits select the prescaler divisor as shown in Table 19-10. Reset clears PDS2-PDS0. NOTE: The setting of `000' will bypass this prescaler. It is not recommended to bypass the prescaler while ENSCI is set, because the switching is not glitch free. Table 19-10. ESCI Prescaler Division Ratio
PS[2:1:0] 000 Prescaler Divisor (PD) Bypass this prescaler 2 3 4 5 6 7 8
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001 010 011 100 101 110 111
PSSB4-PSSB0 -- Clock Insertion Select Bits These read/write bits select the number of clocks inserted in each 32 output cycle frame to achieve more timing resolution on the average prescaler frequency as shown in Table 19-11. Reset clears PSSB4-PSSB0. Use the following formula to calculate the ESCI baud rate: f Bus Baud rate = ----------------------------------------------------------------------------------64 x BPD x BD x ( PD + PDFA ) where: fBus = Bus frequency BPD = Baud rate register prescaler divisor BD = Baud rate divisor PD = Prescaler divisor PDFA = Prescaler divisor fine adjust Table 19-12 shows the ESCI baud rates that can be generated with a 4.9152-MHz bus frequency.
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Table 19-11. ESCI Prescaler Divisor Fine Adjust
PSSB[4:3:2:1:0] 00000 00001 00010 00011 00100 00101 00110 Prescaler Divisor Fine Adjust (PDFA) 0/32 = 0 1/32 = 0.03125 2/32 = 0.0625 3/32 = 0.09375 4/32 = 0.125 5/32 = 0.15625 6/32 = 0.1875 7/32 = 0.21875 8/32 = 0.25 9/32 = 0.28125 10/32 = 0.3125 11/32 = 0.34375 12/32 = 0.375 13/32 = 0.40625 14/32 = 0.4375 15/32 = 0.46875 16/32 = 0.5 17/32 = 0.53125 18/32 = 0.5625 19/32 = 0.59375 20/32 = 0.625 21/32 = 0.65625 22/32 = 0.6875 23/32 = 0.71875 24/32 = 0.75 25/32 = 0.78125 26/32 = 0.8125 27/32 = 0.84375 28/32 = 0.875 29/32 = 0.90625 30/32 = 0.9375 31/32 = 0.96875
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00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111
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Table 19-12. ESCI Baud Rate Selection Examples
PS[2:1:0] 000 111 111 111 111 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 PSSB[4:3:2:1:0] XXXXX 00000 00001 00010 11111 XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX XXXXX SCP[1:0] 00 00 00 00 00 00 00 00 00 00 00 00 01 01 01 01 01 01 01 01 10 10 10 10 10 10 10 10 11 11 11 11 11 11 11 11 Prescaler Divisor (BPD) 1 1 1 1 1 1 1 1 1 1 1 1 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 13 13 13 13 13 13 13 13 SCR[2:1:0] 000 000 000 000 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 Baud Rate Divisor (BD) 1 1 1 1 1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128 1 2 4 8 16 32 64 128 Baud Rate (fBus= 4.9152 MHz) 76,800 9600 9562.65 9525.58 8563.07 38,400 19,200 9600 4800 2400 1200 600 25,600 12,800 6400 3200 1600 800 400 200 19,200 9600 4800 2400 1200 600 300 150 5908 2954 1477 739 369 185 92 46
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19.9 ESCI Arbiter
The ESCI module comprises an arbiter module designed to support software for communication tasks as bus arbitration, baud rate recovery and break time detection. The arbiter module consists of an 9-bit counter with 1-bit overflow and control logic. The CPU can control operation mode via the ESCI arbiter control register (SCIACTL). 19.9.1 ESCI Arbiter Control Register
Address: $000A Bit 7 Read: Write: Reset: AM1 0 6 ALOST 0 5 AM0 0 4 ACLK 0 3 AFIN 0 2 ARUN 0 1 AROVFL 0 Bit 0 ARD8 0
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= Unimplemented
Figure 19-18. ESCI Arbiter Control Register (SCIACTL) AM1 and AM0 -- Arbiter Mode Select Bits These read/write bits select the mode of the arbiter module as shown in Table 19-13. Reset clears AM1 and AM0. Table 19-13. ESCI Arbiter Selectable Modes
AM[1:0] 00 01 10 11 ESCI Arbiter Mode Idle / counter reset Bit time measurement Bus arbitration Reserved / do not use
ALOST -- Arbitration Lost Flag This read-only bit indicates loss of arbitration. Clear ALOST by writing a logic 0 to AM1. Reset clears ALOST. ACLK -- Arbiter Counter Clock Select Bit This read/write bit selects the arbiter counter clock source. Reset clears ACLK. 1 = Arbiter counter is clocked with one half of the ESCI input clock generated by the ESCI prescaler 0 = Arbiter counter is clocked with one half of the bus clock AFIN-- Arbiter Bit Time Measurement Finish Flag This read-only bit indicates bit time measurement has finished. Clear AFIN by writing any value to SCIACTL. Reset clears AFIN. 1 = Bit time measurement has finished 0 = Bit time measurement not yet finished
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ARUN-- Arbiter Counter Running Flag This read-only bit indicates the arbiter counter is running. Reset clears ARUN. 1 = Arbiter counter running 0 = Arbiter counter stopped AROVFL-- Arbiter Counter Overflow Bit This read-only bit indicates an arbiter counter overflow. Clear AROVFL by writing any value to SCIACTL. Writing logic 0s to AM1 and AM0 resets the counter keeps it in this idle state. Reset clears AROVFL. 1 = Arbiter counter overflow has occurred 0 = No arbiter counter overflow has occurred ARD8-- Arbiter Counter MSB This read-only bit is the MSB of the 9-bit arbiter counter. Clear ARD8 by writing any value to SCIACTL. Reset clears ARD8. 19.9.2 ESCI Arbiter Data Register
Address: $000B Bit 7 Read: Write: Reset: 0 0 0 0 0 0 0 0 = Unimplemented ARD7 6 ARD6 5 ARD5 4 ARD4 3 ARD3 2 ARD2 1 ARD1 Bit 0 ARD0
Figure 19-19. ESCI Arbiter Data Register (SCIADAT) ARD7-ARD0 -- Arbiter Least Significant Counter Bits These read-only bits are the eight LSBs of the 9-bit arbiter counter. Clear ARD7-ARD0 by writing any value to SCIACTL. Writing logic 0s to AM1 and AM0 permanently resets the counter and keeps it in this idle state. Reset clears ARD7-ARD0. 19.9.3 Bit Time Measurement Two bit time measurement modes, described here, are available according to the state of ACLK. 1. ACLK = 0 -- The counter is clocked with one half of the bus clock. The counter is started when a falling edge on the RxD pin is detected. The counter will be stopped on the next falling edge. ARUN is set while the counter is running, AFIN is set on the second falling edge on RxD (for instance, the counter is stopped). This mode is used to recover the received baud rate. See Figure 19-20. 2. ACLK = 1 -- The counter is clocked with one half of the ESCI input clock generated by the ESCI prescaler. The counter is started when a logic 0 is detected on RxD (see Figure 19-21). A logic 0 on RxD on enabling the bit time measurement with ACLK = 1 leads to immediate start of the counter (see Figure 19-22). The counter will be stopped on the next rising edge of RxD. This mode is used to measure the length of a received break.
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MEASURED TIME RXD
COUNTER STARTS, ARUN = 1
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Figure 19-20. Bit Time Measurement with ACLK = 0
CPU WRITES SCIACTL WITH $20
MEASURED TIME RXD
CPU WRITES SCIACTL WITH $30 COUNTER STARTS, ARUN = 1
Figure 19-21. Bit Time Measurement with ACLK = 1, Scenario A
MEASURED TIME RXD
COUNTER STARTS, ARUN = 1
COUNTER STOPS, AFIN = 1
Figure 19-22. Bit Time Measurement with ACLK = 1, Scenario B
Data Sheet 252 Enhanced Serial Communications Interface (ESCI) Module
CPU WRITES SCIACTL WITH $30
CPU READS RESULT OUT OF SCIADAT
COUNTER STOPS, AFIN = 1
CPU READS RESULT OUT OF SCIADAT
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CPU READS RESULT OUT OF SCIADAT
COUNTER STOPS, AFIN = 1
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19.9.4 Arbitration Mode If AM[1:0] is set to 10, the arbiter module operates in arbitration mode. On every rising edge of SCI_TxD (output of the ESCI module, internal chip signal), the counter is started. When the counter reaches $38 (ACLK = 0) or $08 (ACLK = 1), RxD is statically sensed. If in this case, RxD is sensed low (for example, another bus is driving the bus dominant) ALOST is set. As long as ALOST is set, the TxD pin is forced to 1, resulting in a seized transmission. If SCI_TxD is sensed logic 0 without having sensed a logic 0 before on RxD, the counter will be reset, arbitration operation will be restarted after the next rising edge of SCI_TxD.
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Data Sheet -- MC68HC908GZ8
Section 20. System Integration Module (SIM)
20.1 Introduction
This section describes the system integration module (SIM). Together with the central processor unit (CPU), the SIM controls all microcontroller unit (MCU) activities. A block diagram of the SIM is shown in Figure 20-1. Table 20-1 is a summary of the SIM input/output (I/O) registers. The SIM is a system state controller that coordinates CPU and exception timing. The SIM is responsible for: * Bus clock generation and control for CPU and peripherals: - Stop/wait/reset/break entry and recovery - Internal clock control Master reset control, including power-on reset (POR) and computer operating properly (COP) timeout Interrupt control: - Acknowledge timing - Arbitration control timing - Vector address generation CPU enable/disable timing Modular architecture expandable to 128 interrupt sources
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* *
* *
Table 20-1 shows the internal signal names used in this section.
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System Integration Module (SIM)
MODULE STOP MODULE WAIT STOP/WAIT CONTROL CPU STOP (FROM CPU) CPU WAIT (FROM CPU) SIMOSCEN (TO CGM) SIM COUNTER CGMXCLK (FROM CGM)
CGMOUT (FROM CGM)
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/2
VDD INTERNAL PULLUP DEVICE RESET PIN LOGIC
CLOCK CONTROL
CLOCK GENERATORS
INTERNAL CLOCKS
FORCED MONITOR MODE ENTRY POR CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER MASTER RESET CONTROL LVI (FROM LVI MODULE) ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP (FROM COP MODULE)
RESET
INTERRUPT CONTROL AND PRIORITY DECODE
INTERRUPT SOURCES CPU INTERFACE
Figure 20-1. SIM Block Diagram Table 20-1. Signal Name Conventions
Signal Name CGMXCLK CGMVCLK CGMOUT IAB IDB PORRST IRST R/W PLL output PLL-based or OSC1-based clock output from CGM module (Bus clock = CGMOUT divided by two) Internal address bus Internal data bus Signal from the power-on reset module to the SIM Internal reset signal Read/write signal Description Buffered version of OSC1 from clock generator module (CGM)
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System Integration Module (SIM) SIM Bus Clock Control and Generation
Addr. $FE00
Register Name SIM Break Status Read: Register (SBSR) Write: See page 271. Reset:
Bit 7 R 0
6 R 0
5 R 0
4 R 0
3 R 0
2 R 0
1 SBSW Note(1) 0
Bit 0 R 0
1. Writing a logic 0 clears SBSW. SIM Reset Status Read: Register (SRSR) Write: See page 272. POR: SIM Break Flag Control Reg- Read: ister (SBFCR) Write: See page 273. Reset: Interrupt Status Read: Register 1 (INT1) Write: See page 267. Reset: Interrupt Status Read: Register 2 (INT2) Write: See page 267. Reset: Interrupt Status Read: Register 3 (INT3) Write: See page 267. Reset: POR 1 BCFE 0 IF6 R 0 IF14 R 0 0 R 0 IF5 R 0 IF13 R 0 0 R 0 = Unimplemented IF4 R 0 IF12 R 0 IF20 R 0 IF3 R 0 IF11 R 0 IF19 R 0 R IF2 R 0 IF10 R 0 IF18 R 0 = Reserved IF1 R 0 IF9 R 0 IF17 R 0 0 R 0 IF8 R 0 IF16 R 0 0 R 0 IF7 R 0 IF15 R 0 PIN 0 R COP 0 R ILOP 0 R ILAD 0 R MODRST 0 R LVI 0 R 0 0 R
$FE01
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$FE03
$FE04
$FE05
$FE06
Figure 20-2. SIM I/O Register Summary
20.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, CGMOUT, as shown in Figure 20-3. This clock originates from either an external oscillator or from the on-chip PLL. 20.2.1 Bus Timing In user mode, the internal bus frequency is either the crystal oscillator output (CGMXCLK) divided by four or the PLL output (CGMVCLK) divided by four. 20.2.2 Clock Startup from POR or LVI Reset When the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 CGMXCLK cycle POR timeout has completed. The RST pin is driven low by the SIM during this entire period. The IBUS clocks start upon completion of the timeout.
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System Integration Module (SIM)
OSC2
OSCILLATOR (OSC)
CGMXCLK OSC1
TO TBM,TIM1,TIM2, ADC, MSCAN
SIM OSCENINSTOP FROM CONFIG
SIMOSCEN IT12 TO REST OF CHIP IT23 TO REST OF CHIP
CGMRCLK CGMOUT PHASE-LOCKED LOOP (PLL)
SIM COUNTER
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/2
BUS CLOCK GENERATORS
TO MSCAN
Figure 20-3. System Clock Signals 20.2.3 Clocks in Stop Mode and Wait Mode Upon exit from stop mode by an interrupt or reset, the SIM allows CGMXCLK to clock the SIM counter. The CPU and peripheral clocks do not become active until after the stop delay timeout. This timeout is selectable as 4096 or 32 CGMXCLK cycles. See 20.6.2 Stop Mode. In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.
20.3 Reset and System Initialization
The MCU has these reset sources: * * * * * * * Power-on reset module (POR) External reset pin (RST) Computer operating properly module (COP) Low-voltage inhibit module (LVI) Illegal opcode Illegal address Forced monitor mode entry reset (MODRST)
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System Integration Module (SIM) Reset and System Initialization
All of these resets produce the vector $FFFE:$FFFF ($FEFE:$FEFF in monitor mode) and assert the internal reset signal (IRST). IRST causes all registers to be returned to their default values and all modules to be returned to their reset states. An internal reset clears the SIM counter (see 20.4 SIM Counter), but an external reset does not. Each of the resets sets a corresponding bit in the SIM reset status register (SRSR). See 20.7 SIM Registers. 20.3.1 External Pin Reset The RST pin circuit includes an internal pullup device. Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for a minimum of 67 CGMXCLK cycles, assuming that neither the POR nor the LVI was the source of the reset. See Table 20-2 for details. Figure 20-4 shows the relative timing. Table 20-2. PIN Bit Set Timing
Reset Type POR/LVI All others Number of Cycles Required to Set PIN 4163 (4096 + 64 + 3) 67 (64 + 3)
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CGMOUT RST IAB PC VECT H VECT L
Figure 20-4. External Reset Timing 20.3.2 Active Resets from Internal Sources All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of external peripherals. The internal reset continues to be asserted for an additional 32 cycles at which point the reset vector will be fetched. See Figure 20-5. An internal reset can be caused by an illegal address, illegal opcode, COP timeout, LVI, or POR. See Figure 20-6. NOTE: For LVI or POR resets, the SIM cycles through 4096 + 32 CGMXCLK cycles during which the SIM forces the RST pin low. The internal reset signal then follows the sequence from the falling edge of RST shown in Figure 20-5. The COP reset is asynchronous to the bus clock.
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System Integration Module (SIM)
RST
RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES
CGMXCLK IAB
VECTOR HIGH
Figure 20-5. Internal Reset Timing
ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST LVI POR MODRST
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INTERNAL RESET
Figure 20-6. Sources of Internal Reset The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU. 20.3.2.1 Power-On Reset When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out 4096 + 32 CGMXCLK cycles. Thirty-two CGMXCLK cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. At power-on, these events occur: * * * * * * A POR pulse is generated. The internal reset signal is asserted. The SIM enables CGMOUT. Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow stabilization of the oscillator. The RST pin is driven low during the oscillator stabilization time. The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are cleared.
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System Integration Module (SIM) Reset and System Initialization
OSC1
PORRST 4096 CYCLES 32 CYCLES
CGMXCLK
CGMOUT
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RST
IAB
$FFFE
$FFFF
Figure 20-7. POR Recovery 20.3.2.2 Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down the RST pin for all internal reset sources. The COP module is disabled if the RST pin or the IRQ pin is held at VTST while the MCU is in monitor mode. The COP module can be disabled only through combinational logic conditioned with the high voltage signal on the RST or the IRQ pin. This prevents the COP from becoming disabled as a result of external noise. During a break state, VTST on the RST pin disables the COP module. 20.3.2.3 Illegal Opcode Reset The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a reset. If the stop enable bit, STOP, in the mask option register is logic 0, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal reset sources. 20.3.2.4 Illegal Address Reset An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down the RST pin for all internal reset sources.
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System Integration Module (SIM)
20.3.2.5 Low-Voltage Inhibit (LVI) Reset The low-voltage inhibit module (LVI) asserts its output to the SIM when the VDD voltage falls to the LVITRIPF voltage. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin (RST) is held low while the SIM counter counts out 4096 + 32 CGMXCLK cycles. Thirty-two CGMXCLK cycles later, the CPU is released from reset to allow the reset vector sequence to occur. The SIM actively pulls down the RST pin for all internal reset sources. 20.3.2.6 Monitor Mode Entry Module Reset (MODRST)
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The monitor mode entry module reset (MODRST) asserts its output to the SIM when monitor mode is entered in the condition where the reset vectors are erased ($FF) (see 15.3.1 Normal Monitor Mode). When MODRST gets asserted, an internal reset occurs. The SIM actively pulls down the RST pin for all internal reset sources.
20.4 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter is 13 bits long. 20.4.1 SIM Counter During Power-On Reset The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit asserts the signal PORRST. Once the SIM is initialized, it enables the clock generation module (CGM) to drive the bus clock state machine. 20.4.2 SIM Counter During Stop Mode Recovery The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the mask option register. If the SSREC bit is a logic 1, then the stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32 CGMXCLK cycles. This is ideal for applications using canned oscillators that do not require long startup times from stop mode. External crystal applications should use the full stop recovery time, that is, with SSREC cleared. 20.4.3 SIM Counter and Reset States External reset has no effect on the SIM counter. See 20.6.2 Stop Mode for details. The SIM counter is free-running after all reset states. See 20.3.2 Active Resets from Internal Sources for counter control and internal reset recovery sequences.
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System Integration Module (SIM) Exception Control
20.5 Exception Control
Normal, sequential program execution can be changed in three different ways: * Interrupts: - Maskable hardware CPU interrupts - Non-maskable software interrupt instruction (SWI) Reset Break interrupts
* * 20.5.1 Interrupts
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At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume. Figure 20-8 shows interrupt entry timing. Figure 20-9 shows interrupt recovery timing.
MODULE INTERRUPT
I BIT
IAB
DUMMY
SP
SP - 1
SP - 2
SP - 3
SP - 4
VECT H
VECT L
START ADDR
IDB
DUMMY
PC - 1[7:0] PC - 1[15:8]
X
A
CCR
V DATA H
V DATA L
OPCODE
R/W
Figure 20-8. Interrupt Entry Timing
MODULE INTERRUPT
I BIT
IAB
SP - 4
SP - 3
SP - 2
SP - 1
SP
PC
PC + 1
IDB
CCR
A
X
PC - 1 [7:0] PC - 1 [15:8] OPCODE
OPERAND
R/W
Figure 20-9. Interrupt Recovery Timing
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System Integration Module (SIM)
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared). See Figure 20-10.
FROM RESET
BREAK I BIT SET? INTERRUPT?
YES
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NO YES
I BIT SET? NO IRQ INTERRUPT? NO YES
AS MANY INTERRUPTS AS EXIST ON CHIP STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR
FETCH NEXT INSTRUCTION
SWI INSTRUCTION? NO RTI INSTRUCTION? NO
YES
YES
UNSTACK CPU REGISTERS
EXECUTE INSTRUCTION
Figure 20-10. Interrupt Processing
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System Integration Module (SIM) Exception Control
20.5.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware interrupts. If interrupts are not masked (I bit clear in the condition code register) and if the corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. Figure 20-11 demonstrates what happens when two interrupts are pending. If an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed.
CLI LDA #$FF BACKGROUND ROUTINE
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INT1
PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI
INT2
PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI
Figure 20-11. Interrupt Recognition Example The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation. NOTE: To maintain compatibility with the M6805 Family, the H register is not pushed on the stack during interrupt entry. If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine.
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System Integration Module (SIM)
20.5.1.2 SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. NOTE: A software interrupt pushes PC onto the stack. A software interrupt does not push PC - 1, as a hardware interrupt does.
20.5.1.3 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources. Table 20-3 summarizes the interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be useful for debugging. Table 20-3. Interrupt Sources
Priority Highest Interrupt Source Reset SWI instruction IRQ pin ICG clock monitor TIM1 channel 0 TIM1 channel 1 TIM1 overflow TIM2 channel 0 TIM2 channel 1 TIM2 overflow SPI receiver full SPI transmitter empty SCI receive error SCI receive SCI transmit Keyboard ADC conversion complete Timebase module MSCAN08 wakeup MSCAN08 error MSCAN08 receive Lowest MSCAN08 transmit Interrupt Status Register Flag -- -- I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 I14 I15 I16 I17 I18 I19 I20
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System Integration Module (SIM) Exception Control
Interrupt Status Register 1
Address: Read: Write: Reset:
$FE04 Bit 7 I6 R 0 R 6 I5 R 0 = Reserved 5 I4 R 0 4 I3 R 0 3 I2 R 0 2 I1 R 0 1 0 R 0 Bit 0 0 R 0
Figure 20-12. Interrupt Status Register 1 (INT1) I6-I1 -- Interrupt Flags 1-6 These flags indicate the presence of interrupt requests from the sources shown in Table 20-3. 1 = Interrupt request present 0 = No interrupt request present Bit 0 and Bit 1 -- Always read 0 Interrupt Status Register 2
Address: Read: Write: Reset: $FE05 Bit 7 I14 R 0 R 6 I13 R 0 = Reserved 5 I12 R 0 4 I11 R 0 3 I10 R 0 2 I9 R 0 1 I8 R 0 Bit 0 I7 R 0
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Figure 20-13. Interrupt Status Register 2 (INT2) I14-I7 -- Interrupt Flags 14-7 These flags indicate the presence of interrupt requests from the sources shown in Table 20-3. 1 = Interrupt request present 0 = No interrupt request present Interrupt Status Register 3
Address: Read: Write: Reset: $FE06 Bit 7 0 R 0 R 6 0 R 0 = Reserved 5 I20 R 0 4 I19 R 0 3 I18 R 0 2 I17 R 0 1 I16 R 0 Bit 0 I15 R 0
Figure 20-14. Interrupt Status Register 3 (INT3) Bits 7-6 -- Always read 0 I20-I15 -- Interrupt Flags 20-15 These flags indicate the presence of an interrupt request from the source shown in Table 20-3. 1 = Interrupt request present 0 = No interrupt request present
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System Integration Module (SIM)
20.5.2 Reset All reset sources always have equal and highest priority and cannot be arbitrated. 20.5.3 Break Interrupts The break module can stop normal program flow at a software-programmable break point by asserting its break interrupt output (see Section 23. Timer Interface Module (TIM)). The SIM puts the CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state.
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20.5.4 Status Flag Protection in Break Mode The SIM controls whether status flags contained in other modules can be cleared during break mode. The user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (BCFE) in the SIM break flag control register (SBFCR). Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This protection allows registers to be freely read and written during break mode without losing status flag information. Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains cleared even when break mode is exited. Status flags with a 2-step clearing mechanism -- for example, a read of one register followed by the read or write of another -- are protected, even when the first step is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step will clear the flag as normal.
20.6 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low power-consumption mode for standby situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is described in the following subsections. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur. 20.6.1 Wait Mode In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 20-15 shows the timing for wait mode entry. A module that is active during wait mode can wakeup the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred. In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is
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System Integration Module (SIM) Low-Power Modes
active or inactive in wait mode. Some modules can be programmed to be active in wait mode. Wait mode also can be exited by a reset (or break in emulation mode). A break interrupt during wait mode sets the SIM break stop/wait bit, SBSW, in the SIM break status register (SBSR). If the COP disable bit, COPD, in the mask option register is logic 0, then the computer operating properly module (COP) is enabled and remains active in wait mode.
IAB WAIT ADDR WAIT ADDR + 1 SAME SAME
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IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
Note:
Previous data can be operand data or the WAIT opcode, depending on the last instruction.
Figure 20-15. Wait Mode Entry Timing Figure 20-16 and Figure 20-17 show the timing for WAIT recovery.
IAB $6E0B $6E0C $00FF $00FE $00FD $00FC
IDB
$A6
$A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
Note: EXITSTOPWAIT = RST pin or CPU interrupt
Figure 20-16. Wait Recovery from Interrupt
32 CYCLES IAB $6E0B 32 CYCLES RSTVCTH RST VCTL
IDB
$A6
$A6
$A6
RST
CGMXCLK
Figure 20-17. Wait Recovery from Internal Reset
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System Integration Module (SIM)
20.6.2 Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time has elapsed. Reset or break also causes an exit from stop mode. The SIM disables the clock generator module outputs (CGMOUT and CGMXCLK) in stop mode, stopping the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the mask option register (MOR). If SSREC is set, stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down to 32. This is ideal for applications using canned oscillators that do not require long startup times from stop mode. NOTE: External crystal applications should use the full stop recovery time by clearing the SSREC bit. The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 20-18 shows stop mode entry timing. Figure 20-19 shows stop mode recovery time from interrupt. NOTE: To minimize stop current, all pins configured as inputs should be driven to a logic 1 or logic 0.
CPUSTOP
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IAB
STOP ADDR
STOP ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W Note: Previous data can be operand data or the STOP opcode, depending on the last instruction.
Figure 20-18. Stop Mode Entry Timing
STOP RECOVERY PERIOD CGMXCLK
INT/BREAK
IAB
STOP +1
STOP + 2
STOP + 2
SP
SP - 1
SP - 2
SP - 3
Figure 20-19. Stop Mode Recovery from Interrupt
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System Integration Module (SIM) SIM Registers
20.7 SIM Registers
The SIM has three memory-mapped registers. Table 20-4 shows the mapping of these registers. Table 20-4. SIM Registers
Address $FE00 $FE01 $FE03 Register SBSR SRSR SBFCR Access Mode User User User
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20.7.1 Break Status Register The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode. This register is only used in emulation mode.
Address: Read: Write: Reset: $FE00 Bit 7 R 0 R 6 R 0 = Reserved 5 R 0 4 R 0 3 R 0 2 R 0 1 SBSW Note(1) 0 Bit 0 R 0
1. Writing a logic 0 clears SBSW.
Figure 20-20. Break Status Register (BSR) SBSW -- SIM Break Stop/Wait SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. 1 = Wait mode was exited by break interrupt. 0 = Wait mode was not exited by break interrupt.
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System Integration Module (SIM)
20.7.2 SIM Reset Status Register This register contains six flags that show the source of the last reset provided all previous reset status bits have been cleared. Clear the SIM reset status register by reading it. A power-on reset sets the POR bit and clears all other bits in the register.
Address: Read: Write: Reset: 1 0 = Unimplemented 0 0 0 0 0 0 $FE01 Bit 7 POR 6 PIN 5 COP 4 ILOP 3 ILAD 2 MODRST 1 LVI Bit 0 0
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Figure 20-21. SIM Reset Status Register (SRSR) POR -- Power-On Reset Bit 1 = Last reset caused by POR circuit 0 = Read of SRSR PIN -- External Reset Bit 1 = Last reset caused by external reset pin (RST) 0 = POR or read of SRSR COP -- Computer Operating Properly Reset Bit 1 = Last reset caused by COP counter 0 = POR or read of SRSR ILOP -- Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR ILAD -- Illegal Address Reset Bit (opcode fetches only) 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR MODRST -- Monitor Mode Entry Module Reset Bit 1 = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after POR while IRQ = VDD 0 = POR or read of SRSR LVI -- Low-Voltage Inhibit Reset Bit 1 = Last reset caused by the LVI circuit 0 = POR or read of SRSR
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System Integration Module (SIM) SIM Registers
20.7.3 Break Flag Control Register The SIM break control register contains a bit that enables software to clear status bits while the MCU is in a break state.
Address: Read: Write: Reset: $FE03 Bit 7 BCFE 0 R = Reserved 6 R 5 R 4 R 3 R 2 R 1 R Bit 0 R
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Figure 20-22. Break Flag Control Register (BFCR) BCFE -- Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break
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System Integration Module (SIM)
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Data Sheet 274 System Integration Module (SIM)
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Data Sheet -- MC68HC908GZ8
Section 21. Serial Peripheral Interface (SPI) Module
21.1 Introduction
This section describes the serial peripheral interface (SPI) module, which allows full-duplex, synchronous, serial communications with peripheral devices.
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21.2 Features
Features of the SPI module include: * * * * * * * Full-duplex operation Master and slave modes Double-buffered operation with separate transmit and receive registers Four master mode frequencies (maximum = bus frequency / 2) Maximum slave mode frequency = bus frequency Serial clock with programmable polarity and phase Two separately enabled interrupts: - SPRF (SPI receiver full) - SPTE (SPI transmitter empty) Mode fault error flag with CPU interrupt capability Overflow error flag with CPU interrupt capability Programmable wired-OR mode I2C (inter-integrated circuit) compatibility I/O (input/output) port bit(s) software configurable with pullup device(s) if configured as input port bit(s)
* * * * *
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Serial Peripheral Interface (SPI) Module
21.3 Pin Name Conventions
The text that follows describes the SPI. The SPI I/O pin names are SS (slave select), SPSCK (SPI serial clock), CGND (clock ground), MOSI (master out slave in), and MISO (master in/slave out). The SPI shares four I/O pins with four parallel I/O ports. The full names of the SPI I/O pins are shown in Table 21-1. The generic pin names appear in the text that follows. Table 21-1. Pin Name Conventions
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SPI Generic Pin Names: Full SPI Pin Names: SPI
MISO PTD1/MISO
MOSI PTD2/MOSI
SS PTD0/SS
SPSCK PTD3/SPSCK
CGND VSS
21.4 Functional Description
Figure 21-1 summarizes the SPI I/O registers and Figure 21-2 shows the structure of the SPI module. The SPI module allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. Software can poll the SPI status flags or SPI operation can be interrupt driven. If a port bit is configured for input, then an internal pullup device may be enabled for that port bit. See 17.4.3 Port C Input Pullup Enable Register. The following paragraphs describe the operation of the SPI module.
Addr. Register Name Bit 7 SPRIE 0 SPRF 0 R7 T7 6 R 0 ERRIE 0 R6 T6 5 SPMSTR 1 OVRF 0 R5 T5 4 CPOL 0 MODF 0 R4 T4 3 CPHA 1 SPTE 1 R3 T3 2 SPWOM 0 MODFEN 0 R2 T2 1 SPE 0 SPR1 0 R1 T1 Bit 0 SPTIE 0 SPR0 0 R0 T0
Read: SPI Control Register (SPCR) Write: $0010 See page 293. Reset: SPI Status and Control Reg- Read: $0011 ister (SPSCR) Write: See page 295. Reset: $0012 SPI Data Register Read: (SPDR) Write: See page 297. Reset:
Unaffected by reset
R = Reserved = Unimplemented
Figure 21-1. SPI I/O Register Summary
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Serial Peripheral Interface (SPI) Module Functional Description
INTERNAL BUS
TRANSMIT DATA REGISTER CGMOUT / 2 FROM SIM 7 /2 CLOCK DIVIDER /8 / 32 / 128 CLOCK SELECT MOSI RECEIVE DATA REGISTER PIN CONTROL LOGIC SPSCK CLOCK LOGIC M S SS 6
SHIFT REGISTER 5 4 3 2 1 0 MISO
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SPMSTR
SPE
SPR1
SPR0
SPMSTR
CPHA
CPOL
RESERVED TRANSMITTER CPU INTERRUPT REQUEST RESERVED RECEIVER/ERROR CPU INTERRUPT REQUEST SPI CONTROL
MODFEN ERRIE SPTIE SPRIE DMAS SPE SPRF SPTE OVRF MODF
SPWOM
Figure 21-2. SPI Module Block Diagram
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Serial Peripheral Interface (SPI) Module
21.4.1 Master Mode The SPI operates in master mode when the SPI master bit, SPMSTR, is set. NOTE: Configure the SPI modules as master or slave before enabling them. Enable the master SPI before enabling the slave SPI. Disable the slave SPI before disabling the master SPI. See 21.13.1 SPI Control Register. Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI module by writing to the transmit data register. If the shift register is empty, the byte immediately transfers to the shift register, setting the SPI transmitter empty bit, SPTE. The byte begins shifting out on the MOSI pin under the control of the serial clock. See Figure 21-3.
MASTER MCU SLAVE MCU
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SHIFT REGISTER
MISO MOSI SPSCK
MISO MOSI SPSCK SS
SHIFT REGISTER
BAUD RATE GENERATOR
SS
VDD
Figure 21-3. Full-Duplex Master-Slave Connections The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register. (See 21.13.2 SPI Status and Control Register.) Through the SPSCK pin, the baud rate generator of the master also controls the shift register of the slave peripheral. As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master's MISO pin. The transmission ends when the receiver full bit, SPRF, becomes set. At the same time that SPRF becomes set, the byte from the slave transfers to the receive data register. In normal operation, SPRF signals the end of a transmission. Software clears SPRF by reading the SPI status and control register with SPRF set and then reading the SPI data register. Writing to the SPI data register clears the SPTE bit. 21.4.2 Slave Mode The SPI operates in slave mode when the SPMSTR bit is clear. In slave mode, the SPSCK pin is the input for the serial clock from the master MCU. Before a data transmission occurs, the SS pin of the slave SPI must be at logic 0. SS must remain low until the transmission is complete. See 21.7.2 Mode Fault Error. In a slave SPI module, data enters the shift register under the control of the serial clock from the master SPI module. After a byte enters the shift register of a slave
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Serial Peripheral Interface (SPI) Module Transmission Formats
SPI, it transfers to the receive data register, and the SPRF bit is set. To prevent an overflow condition, slave software then must read the receive data register before another full byte enters the shift register. The maximum frequency of the SPSCK for an SPI configured as a slave is the bus clock speed (which is twice as fast as the fastest master SPSCK clock that can be generated). The frequency of the SPSCK for an SPI configured as a slave does not have to correspond to any SPI baud rate. The baud rate only controls the speed of the SPSCK generated by an SPI configured as a master. Therefore, the frequency of the SPSCK for an SPI configured as a slave can be any frequency less than or equal to the bus speed.
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When the master SPI starts a transmission, the data in the slave shift register begins shifting out on the MISO pin. The slave can load its shift register with a new byte for the next transmission by writing to its transmit data register. The slave must write to its transmit data register at least one bus cycle before the master starts the next transmission. Otherwise, the byte already in the slave shift register shifts out on the MISO pin. Data written to the slave shift register during a transmission remains in a buffer until the end of the transmission. When the clock phase bit (CPHA) is set, the first edge of SPSCK starts a transmission. When CPHA is clear, the falling edge of SS starts a transmission. See 21.5 Transmission Formats. NOTE: SPSCK must be in the proper idle state before the slave is enabled to prevent SPSCK from appearing as a clock edge.
21.5 Transmission Formats
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock synchronizes shifting and sampling on the two serial data lines. A slave select line allows selection of an individual slave SPI device; slave devices that are not selected do not interfere with SPI bus activities. On a master SPI device, the slave select line can optionally be used to indicate multiple-master bus contention. 21.5.1 Clock Phase and Polarity Controls Software can select any of four combinations of serial clock (SPSCK) phase and polarity using two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active high or low clock and has no significant effect on the transmission format. The clock phase (CPHA) control bit selects one of two fundamentally different transmission formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements.
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Serial Peripheral Interface (SPI) Module
NOTE: Before writing to the CPOL bit or the CPHA bit, disable the SPI by clearing the SPI enable bit (SPE).
21.5.2 Transmission Format When CPHA = 0 Figure 21-4 shows an SPI transmission in which CPHA is logic 0. The figure should not be used as a replacement for data sheet parametric information. Two waveforms are shown for SPSCK: one for CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing diagram since the serial clock (SPSCK), master in/slave out (MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select input (SS) is at logic 0, so that only the selected slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS pin of the master must be high or must be reconfigured as general-purpose I/O not affecting the SPI. (See 21.7.2 Mode Fault Error.) When CPHA = 0, the first SPSCK edge is the MSB capture strobe. Therefore, the slave must begin driving its data before the first SPSCK edge, and a falling edge on the SS pin is used to start the slave data transmission. The slave's SS pin must be toggled back to high and then low again between each byte transmitted as shown in Figure 21-5.
SPSCK CYCLE # FOR REFERENCE SPSCK; CPOL = 0 SPSCK; CPOL =1 MOSI FROM MASTER MISO FROM SLAVE SS; TO SLAVE CAPTURE STROBE MSB MSB BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 LSB LSB 1 2 3 4 5 6 7 8
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Figure 21-4. Transmission Format (CPHA = 0)
MISO/MOSI MASTER SS SLAVE SS CPHA = 0 SLAVE SS CPHA = 1 BYTE 1 BYTE 2 BYTE 3
Figure 21-5. CPHA/SS Timing
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Serial Peripheral Interface (SPI) Module Transmission Formats
When CPHA = 0 for a slave, the falling edge of SS indicates the beginning of the transmission. This causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the transmission begins, no new data is allowed into the shift register from the transmit data register. Therefore, the SPI data register of the slave must be loaded with transmit data before the falling edge of SS. Any data written after the falling edge is stored in the transmit data register and transferred to the shift register after the current transmission. 21.5.3 Transmission Format When CPHA = 1 Figure 21-6 shows an SPI transmission in which CPHA is logic 1. The figure should not be used as a replacement for data sheet parametric information. Two waveforms are shown for SPSCK: one for CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing diagram since the serial clock (SPSCK), master in/slave out (MISO), and master out/slave in (MOSI) pins are directly connected between the master and the slave. The MISO signal is the output from the slave, and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The slave SPI drives its MISO output only when its slave select input (SS) is at logic 0, so that only the selected slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS pin of the master must be high or must be reconfigured as general-purpose I/O not affecting the SPI. (See 21.7.2 Mode Fault Error.) When CPHA = 1, the master begins driving its MOSI pin on the first SPSCK edge. Therefore, the slave uses the first SPSCK edge as a start transmission signal. The SS pin can remain low between transmissions. This format may be preferable in systems having only one master and only one slave driving the MISO data line. When CPHA = 1 for a slave, the first edge of the SPSCK indicates the beginning of the transmission. This causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data. Once the transmission begins, no new data is allowed into the shift register from the transmit data register. Therefore, the SPI data register of the slave must be loaded with transmit data before the first edge of SPSCK. Any data written after the first edge is stored in the transmit data register and transferred to the shift register after the current transmission.
SPSCK CYCLE # FOR REFERENCE SPSCK; CPOL = 0 SPSCK; CPOL =1 MOSI FROM MASTER MISO FROM SLAVE SS; TO SLAVE CAPTURE STROBE MSB MSB BIT 6 BIT 6 BIT 5 BIT 5 BIT 4 BIT 4 BIT 3 BIT 3 BIT 2 BIT 2 BIT 1 BIT 1 LSB LSB 1 2 3 4 5 6 7 8
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Figure 21-6. Transmission Format (CPHA = 1)
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Serial Peripheral Interface (SPI) Module
21.5.4 Transmission Initiation Latency When the SPI is configured as a master (SPMSTR = 1), writing to the SPDR starts a transmission. CPHA has no effect on the delay to the start of the transmission, but it does affect the initial state of the SPSCK signal. When CPHA = 0, the SPSCK signal remains inactive for the first half of the first SPSCK cycle. When CPHA = 1, the first SPSCK cycle begins with an edge on the SPSCK line from its inactive to its active level. The SPI clock rate (selected by SPR1:SPR0) affects the delay from the write to SPDR and the start of the SPI transmission. (See Figure 21-7.)
WRITE TO SPDR INITIATION DELAY
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BUS CLOCK MOSI SPSCK CPHA = 1 SPSCK CPHA = 0 SPSCK CYCLE NUMBER 1 2 3
MSB
BIT 6
BIT 5
INITIATION DELAY FROM WRITE SPDR TO TRANSFER BEGIN
WRITE TO SPDR BUS CLOCK EARLIEST WRITE TO SPDR BUS CLOCK EARLIEST WRITE TO SPDR BUS CLOCK EARLIEST WRITE TO SPDR BUS CLOCK EARLIEST SPSCK = INTERNAL CLOCK / 128; 128 POSSIBLE START POINTS LATEST SPSCK = INTERNAL CLOCK / 32; 32 POSSIBLE START POINTS LATEST SPSCK = INTERNAL CLOCK / 8; 8 POSSIBLE START POINTS LATEST LATEST SPSCK = INTERNAL CLOCK / 2; 2 POSSIBLE START POINTS
Figure 21-7. Transmission Start Delay (Master)
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Serial Peripheral Interface (SPI) Module Queuing Transmission Data
The internal SPI clock in the master is a free-running derivative of the internal MCU clock. To conserve power, it is enabled only when both the SPE and SPMSTR bits are set. SPSCK edges occur halfway through the low time of the internal MCU clock. Since the SPI clock is free-running, it is uncertain where the write to the SPDR occurs relative to the slower SPSCK. This uncertainty causes the variation in the initiation delay shown in Figure 21-7. This delay is no longer than a single SPI bit time. That is, the maximum delay is two MCU bus cycles for DIV2, eight MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU bus cycles for DIV128.
21.6 Queuing Transmission Data
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The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. The SPI transmitter empty flag (SPTE) indicates when the transmit data buffer is ready to accept new data. Write to the transmit data register only when the SPTE bit is high. Figure 21-8 shows the timing associated with doing back-to-back transmissions with the SPI (SPSCK has CPHA: CPOL = 1:0).
WRITE TO SPDR SPTE SPSCK CPHA:CPOL = 1:0 MOSI MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT BIT BIT BIT LSB MSB BIT BIT BIT 654 654321 654321 BYTE 1 BYTE 2 BYTE 3 4 6 7 7 CPU READS SPDR, CLEARING SPRF BIT. 8 CPU WRITES BYTE 3 TO SPDR, QUEUEING BYTE 3 AND CLEARING SPTE BIT. 9 SECOND INCOMING BYTE TRANSFERS FROM SHIFT REGISTER TO RECEIVE DATA REGISTER, SETTING SPRF BIT. 10 BYTE 3 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. 11 CPU READS SPSCR WITH SPRF BIT SET. 12 CPU READS SPDR, CLEARING SPRF BIT. 9 11 12 1 2 3 5 8 10
SPRF READ SPSCR READ SPDR 1 CPU WRITES BYTE 1 TO SPDR, CLEARING SPTE BIT. 2 BYTE 1 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. 3 CPU WRITES BYTE 2 TO SPDR, QUEUEING BYTE 2 AND CLEARING SPTE BIT. 4 FIRST INCOMING BYTE TRANSFERS FROM SHIFT REGISTER TO RECEIVE DATA REGISTER, SETTING SPRF BIT. 5 BYTE 2 TRANSFERS FROM TRANSMIT DATA REGISTER TO SHIFT REGISTER, SETTING SPTE BIT. 6 CPU READS SPSCR WITH SPRF BIT SET.
Figure 21-8. SPRF/SPTE CPU Interrupt Timing
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Serial Peripheral Interface (SPI) Module
The transmit data buffer allows back-to-back transmissions without the slave precisely timing its writes between transmissions as in a system with a single data buffer. Also, if no new data is written to the data buffer, the last value contained in the shift register is the next data word to be transmitted. For an idle master or idle slave that has no data loaded into its transmit buffer, the SPTE is set again no more than two bus cycles after the transmit buffer empties into the shift register. This allows the user to queue up a 16-bit value to send. For an already active slave, the load of the shift register cannot occur until the transmission is completed. This implies that a back-to-back write to the transmit data register is not possible. The SPTE indicates when the next write can occur.
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21.7 Error Conditions
The following flags signal SPI error conditions: * Overflow (OVRF) -- Failing to read the SPI data register before the next full byte enters the shift register sets the OVRF bit. The new byte does not transfer to the receive data register, and the unread byte still can be read. OVRF is in the SPI status and control register. * Mode fault error (MODF) -- The MODF bit indicates that the voltage on the slave select pin (SS) is inconsistent with the mode of the SPI. MODF is in the SPI status and control register. 21.7.1 Overflow Error The overflow flag (OVRF) becomes set if the receive data register still has unread data from a previous transmission when the capture strobe of bit 1 of the next transmission occurs. The bit 1 capture strobe occurs in the middle of SPSCK cycle 7 (see Figure 21-4 and Figure 21-6.) If an overflow occurs, all data received after the overflow and before the OVRF bit is cleared does not transfer to the receive data register and does not set the SPI receiver full bit (SPRF). The unread data that transferred to the receive data register before the overflow occurred can still be read. Therefore, an overflow error always indicates the loss of data. Clear the overflow flag by reading the SPI status and control register and then reading the SPI data register. OVRF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector (see Figure 21-11.) It is not possible to enable MODF or OVRF individually to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set. If the CPU SPRF interrupt is enabled and the OVRF interrupt is not, watch for an overflow condition. Figure 21-9 shows how it is possible to miss an overflow. The first part of Figure 21-9 shows how it is possible to read the SPSCR and SPDR to clear the SPRF without problems. However, as illustrated by the second transmission example, the OVRF bit can be set in between the time that SPSCR and SPDR are read.
Data Sheet 284 Serial Peripheral Interface (SPI) Module MC68HC908GZ8 MOTOROLA
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Serial Peripheral Interface (SPI) Module Error Conditions
BYTE 1 1
BYTE 2 4
BYTE 3 6
BYTE 4 8
SPRF
OVRF READ SPSCR READ SPDR 2 5
3 1 2 3 4 BYTE 1 SETS SPRF BIT. CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT. BYTE 2 SETS SPRF BIT. 5 6 7 8
7 CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST. CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT, BUT NOT OVRF BIT. BYTE 4 FAILS TO SET SPRF BIT BECAUSE OVRF BIT IS NOT CLEARED. BYTE 4 IS LOST.
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Figure 21-9. Missed Read of Overflow Condition In this case, an overflow can be missed easily. Since no more SPRF interrupts can be generated until this OVRF is serviced, it is not obvious that bytes are being lost as more transmissions are completed. To prevent this, either enable the OVRF interrupt or do another read of the SPSCR following the read of the SPDR. This ensures that the OVRF was not set before the SPRF was cleared and that future transmissions can set the SPRF bit. Figure 21-10 illustrates this process. Generally, to avoid this second SPSCR read, enable the OVRF to the CPU by setting the ERRIE bit. 21.7.2 Mode Fault Error Setting the SPMSTR bit selects master mode and configures the SPSCK and MOSI pins as outputs and the MISO pin as an input. Clearing SPMSTR selects slave mode and configures the SPSCK and MOSI pins as inputs and the MISO pin as an output. The mode fault bit, MODF, becomes set any time the state of the slave select pin, SS, is inconsistent with the mode selected by SPMSTR. To prevent SPI pin contention and damage to the MCU, a mode fault error occurs if: * * The SS pin of a slave SPI goes high during a transmission The SS pin of a master SPI goes low at any time
For the MODF flag to be set, the mode fault error enable bit (MODFEN) must be set. Clearing the MODFEN bit does not clear the MODF flag but does prevent MODF from being set again after MODF is cleared.
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Serial Peripheral Interface (SPI) Module
BYTE 1 SPI RECEIVE COMPLETE SPRF OVRF READ SPSCR READ SPDR 1 2 3 4 1
BYTE 2 5
BYTE 3 7
BYTE 4 11
6 8 8 9
9 10
12 13
14
BYTE 1 SETS SPRF BIT. CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. CPU READS BYTE 1 IN SPDR, CLEARING SPRF BIT. CPU READS SPSCR AGAIN TO CHECK OVRF BIT. BYTE 2 SETS SPRF BIT. CPU READS SPSCR WITH SPRF BIT SET AND OVRF BIT CLEAR. BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
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2 3 4 5 6 7
CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT. CPU READS SPSCR AGAIN TO CHECK OVRF BIT.
10 CPU READS BYTE 2 SPDR, CLEARING OVRF BIT. 11 BYTE 4 SETS SPRF BIT. 12 CPU READS SPSCR. 13 CPU READS BYTE 4 IN SPDR, CLEARING SPRF BIT. 14 CPU READS SPSCR AGAIN TO CHECK OVRF BIT.
Figure 21-10. Clearing SPRF When OVRF Interrupt Is Not Enabled MODF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. (See Figure 21-11.) It is not possible to enable MODF or OVRF individually to generate a receiver/error CPU interrupt request. However, leaving MODFEN low prevents MODF from being set. In a master SPI with the mode fault enable bit (MODFEN) set, the mode fault flag (MODF) is set if SS goes to logic 0. A mode fault in a master SPI causes the following events to occur: * If ERRIE = 1, the SPI generates an SPI receiver/error CPU interrupt request. * The SPE bit is cleared. * The SPTE bit is set. * The SPI state counter is cleared. * The data direction register of the shared I/O port regains control of port drivers. NOTE: To prevent bus contention with another master SPI after a mode fault error, clear all SPI bits of the data direction register of the shared I/O port before enabling the SPI. When configured as a slave (SPMSTR = 0), the MODF flag is set if SS goes high during a transmission. When CPHA = 0, a transmission begins when SS goes low and ends once the incoming SPSCK goes back to its idle level following the shift
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Serial Peripheral Interface (SPI) Module Interrupts
of the eighth data bit. When CPHA = 1, the transmission begins when the SPSCK leaves its idle level and SS is already low. The transmission continues until the SPSCK returns to its idle level following the shift of the last data bit. See 21.5 Transmission Formats. NOTE: Setting the MODF flag does not clear the SPMSTR bit. The SPMSTR bit has no function when SPE = 0. Reading SPMSTR when MODF = 1 shows the difference between a MODF occurring when the SPI is a master and when it is a slave. When CPHA = 0, a MODF occurs if a slave is selected (SS is at logic 0) and later unselected (SS is at logic 1) even if no SPSCK is sent to that slave. This happens because SS at logic 0 indicates the start of the transmission (MISO driven out with the value of MSB) for CPHA = 0. When CPHA = 1, a slave can be selected and then later unselected with no transmission occurring. Therefore, MODF does not occur since a transmission was never begun. In a slave SPI (MSTR = 0), the MODF bit generates an SPI receiver/error CPU interrupt request if the ERRIE bit is set. The MODF bit does not clear the SPE bit or reset the SPI in any way. Software can abort the SPI transmission by clearing the SPE bit of the slave. NOTE: A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high impedance state. Also, the slave SPI ignores all incoming SPSCK clocks, even if it was already in the middle of a transmission. To clear the MODF flag, read the SPSCR with the MODF bit set and then write to the SPCR register. This entire clearing mechanism must occur with no MODF condition existing or else the flag is not cleared.
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21.8 Interrupts
Four SPI status flags can be enabled to generate CPU interrupt requests. See Table 21-2. Table 21-2. SPI Interrupts
Flag SPTE Transmitter empty SPRF Receiver full OVRF Overflow MODF Mode fault Request SPI transmitter CPU interrupt request (DMAS = 0, SPTIE = 1, SPE = 1) SPI receiver CPU interrupt request (DMAS = 0, SPRIE = 1) SPI receiver/error interrupt request (ERRIE = 1) SPI receiver/error interrupt request (ERRIE = 1)
Reading the SPI status and control register with SPRF set and then reading the receive data register clears SPRF. The clearing mechanism for the SPTE flag is always just a write to the transmit data register.
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The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate transmitter CPU interrupt requests, provided that the SPI is enabled (SPE = 1). The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to generate receiver CPU interrupt requests, regardless of the state of the SPE bit. See Figure 21-11. The error interrupt enable bit (ERRIE) enables both the MODF and OVRF bits to generate a receiver/error CPU interrupt request. The mode fault enable bit (MODFEN) can prevent the MODF flag from being set so that only the OVRF bit is enabled by the ERRIE bit to generate receiver/error CPU interrupt requests.
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NOT AVAILABLE
SPTE
SPTIE
SPE SPI TRANSMITTER CPU INTERRUPT REQUEST
DMAS
NOT AVAILABLE
SPRIE
SPRF
SPI RECEIVER/ERROR ERRIE MODF OVRF CPU INTERRUPT REQUEST
Figure 21-11. SPI Interrupt Request Generation The following sources in the SPI status and control register can generate CPU interrupt requests: * SPI receiver full bit (SPRF) -- The SPRF bit becomes set every time a byte transfers from the shift register to the receive data register. If the SPI receiver interrupt enable bit, SPRIE, is also set, SPRF generates an SPI receiver/error CPU interrupt request. SPI transmitter empty (SPTE) -- The SPTE bit becomes set every time a byte transfers from the transmit data register to the shift register. If the SPI transmit interrupt enable bit, SPTIE, is also set, SPTE generates an SPTE CPU interrupt request.
*
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Serial Peripheral Interface (SPI) Module Resetting the SPI
21.9 Resetting the SPI
Any system reset completely resets the SPI. Partial resets occur whenever the SPI enable bit (SPE) is low. Whenever SPE is low, the following occurs: * * * * * The SPTE flag is set. Any transmission currently in progress is aborted. The shift register is cleared. The SPI state counter is cleared, making it ready for a new complete transmission. All the SPI port logic is defaulted back to being general-purpose I/O. All control bits in the SPCR register All control bits in the SPSCR register (MODFEN, ERRIE, SPR1, and SPR0) The status flags SPRF, OVRF, and MODF
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These items are reset only by a system reset: * * *
By not resetting the control bits when SPE is low, the user can clear SPE between transmissions without having to set all control bits again when SPE is set back high for the next transmission. By not resetting the SPRF, OVRF, and MODF flags, the user can still service these interrupts after the SPI has been disabled. The user can disable the SPI by writing 0 to the SPE bit. The SPI can also be disabled by a mode fault occurring in an SPI that was configured as a master with the MODFEN bit set.
21.10 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 21.10.1 Wait Mode The SPI module remains active after the execution of a WAIT instruction. In wait mode the SPI module registers are not accessible by the CPU. Any enabled CPU interrupt request from the SPI module can bring the MCU out of wait mode. If SPI module functions are not required during wait mode, reduce power consumption by disabling the SPI module before executing the WAIT instruction. To exit wait mode when an overflow condition occurs, enable the OVRF bit to generate CPU interrupt requests by setting the error interrupt enable bit (ERRIE). See 21.8 Interrupts.
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21.10.2 Stop Mode The SPI module is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions. SPI operation resumes after an external interrupt. If stop mode is exited by reset, any transfer in progress is aborted, and the SPI is reset.
21.11 SPI During Break Interrupts
The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. See Section 20. System Integration Module (SIM). To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit. Since the SPTE bit cannot be cleared during a break with the BCFE bit cleared, a write to the transmit data register in break mode does not initiate a transmission nor is this data transferred into the shift register. Therefore, a write to the SPDR in break mode with the BCFE bit cleared has no effect.
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21.12 I/O Signals
The SPI module has five I/O pins and shares four of them with a parallel I/O port. They are: * * * * * MISO -- Data received MOSI -- Data transmitted SPSCK -- Serial clock SS -- Slave select CGND -- Clock ground (internally connected to VSS)
The SPI has limited inter-integrated circuit (I2C) capability (requiring software support) as a master in a single-master environment. To communicate with I2C peripherals, MOSI becomes an open-drain output when the SPWOM bit in the SPI control register is set. In I2C communication, the MOSI and MISO pins are connected to a bidirectional pin from the I2C peripheral and through a pullup resistor to VDD.
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Serial Peripheral Interface (SPI) Module I/O Signals
21.12.1 MISO (Master In/Slave Out) MISO is one of the two SPI module pins that transmits serial data. In full duplex operation, the MISO pin of the master SPI module is connected to the MISO pin of the slave SPI module. The master SPI simultaneously receives data on its MISO pin and transmits data from its MOSI pin. Slave output data on the MISO pin is enabled only when the SPI is configured as a slave. The SPI is configured as a slave when its SPMSTR bit is logic 0 and its SS pin is at logic 0. To support a multiple-slave system, a logic 1 on the SS pin puts the MISO pin in a high-impedance state.
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When enabled, the SPI controls data direction of the MISO pin regardless of the state of the data direction register of the shared I/O port. 21.12.2 MOSI (Master Out/Slave In) MOSI is one of the two SPI module pins that transmits serial data. In full-duplex operation, the MOSI pin of the master SPI module is connected to the MOSI pin of the slave SPI module. The master SPI simultaneously transmits data from its MOSI pin and receives data on its MISO pin. When enabled, the SPI controls data direction of the MOSI pin regardless of the state of the data direction register of the shared I/O port. 21.12.3 SPSCK (Serial Clock) The serial clock synchronizes data transmission between master and slave devices. In a master MCU, the SPSCK pin is the clock output. In a slave MCU, the SPSCK pin is the clock input. In full-duplex operation, the master and slave MCUs exchange a byte of data in eight serial clock cycles. When enabled, the SPI controls data direction of the SPSCK pin regardless of the state of the data direction register of the shared I/O port. 21.12.4 SS (Slave Select) The SS pin has various functions depending on the current state of the SPI. For an SPI configured as a slave, the SS is used to select a slave. For CPHA = 0, the SS is used to define the start of a transmission. (See 21.5 Transmission Formats.) Since it is used to indicate the start of a transmission, the SS must be toggled high and low between each byte transmitted for the CPHA = 0 format. However, it can remain low between transmissions for the CPHA = 1 format. See Figure 21-12.
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Serial Peripheral Interface (SPI) Module
MISO/MOSI MASTER SS SLAVE SS CPHA = 0 SLAVE SS CPHA = 1
BYTE 1
BYTE 2
BYTE 3
Figure 21-12. CPHA/SS Timing When an SPI is configured as a slave, the SS pin is always configured as an input. It cannot be used as a general-purpose I/O regardless of the state of the MODFEN control bit. However, the MODFEN bit can still prevent the state of the SS from creating a MODF error. See 21.13.2 SPI Status and Control Register. NOTE: A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high-impedance state. The slave SPI ignores all incoming SPSCK clocks, even if it was already in the middle of a transmission. When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to prevent multiple masters from driving MOSI and SPSCK. (See 21.7.2 Mode Fault Error.) For the state of the SS pin to set the MODF flag, the MODFEN bit in the SPSCK register must be set. If the MODFEN bit is low for an SPI master, the SS pin can be used as a general-purpose I/O under the control of the data direction register of the shared I/O port. With MODFEN high, it is an input-only pin to the SPI regardless of the state of the data direction register of the shared I/O port. The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and reading the port data register. See Table 21-3. Table 21-3. SPI Configuration
SPE 0 1 1 1 SPMSTR X(1)) 0 1 1 MODFEN X X 0 1 SPI Configuration Not enabled Slave Master without MODF Master with MODF State of SS Logic General-purpose I/O; SS ignored by SPI Input-only to SPI General-purpose I/O; SS ignored by SPI Input-only to SPI
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1. X = Don't care
Data Sheet 292 Serial Peripheral Interface (SPI) Module
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Serial Peripheral Interface (SPI) Module I/O Registers
21.12.5 CGND (Clock Ground) CGND is the ground return for the serial clock pin, SPSCK, and the ground for the port output buffers. It is internally connected to VSS as shown in Table 21-1.
21.13 I/O Registers
Three registers control and monitor SPI operation: * * * SPI control register (SPCR) SPI status and control register (SPSCR) SPI data register (SPDR)
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21.13.1 SPI Control Register The SPI control register: * * * * * Enables SPI module interrupt requests Configures the SPI module as master or slave Selects serial clock polarity and phase Configures the SPSCK, MOSI, and MISO pins as open-drain outputs Enables the SPI module
Address: $0010 Bit 7 Read: Write: Reset: SPRIE 0 R 6 R 0 = Reserved 5 SPMSTR 1 4 CPOL 0 3 CPHA 1 2 SPWOM 0 = Unimplemented 1 SPE 0 Bit 0 SPTIE 0
Figure 21-13. SPI Control Register (SPCR) SPRIE -- SPI Receiver Interrupt Enable Bit This read/write bit enables CPU interrupt requests generated by the SPRF bit. The SPRF bit is set when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit. 1 = SPRF CPU interrupt requests enabled 0 = SPRF CPU interrupt requests disabled SPMSTR -- SPI Master Bit This read/write bit selects master mode operation or slave mode operation. Reset sets the SPMSTR bit. 1 = Master mode 0 = Slave mode
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CPOL -- Clock Polarity Bit This read/write bit determines the logic state of the SPSCK pin between transmissions. (See Figure 21-4 and Figure 21-6.) To transmit data between SPI modules, the SPI modules must have identical CPOL values. Reset clears the CPOL bit. CPHA -- Clock Phase Bit This read/write bit controls the timing relationship between the serial clock and SPI data. (See Figure 21-4 and Figure 21-6.) To transmit data between SPI modules, the SPI modules must have identical CPHA values. When CPHA = 0, the SS pin of the slave SPI module must be set to logic 1 between bytes. (See Figure 21-12.) Reset sets the CPHA bit.
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SPWOM -- SPI Wired-OR Mode Bit This read/write bit disables the pullup devices on pins SPSCK, MOSI, and MISO so that those pins become open-drain outputs. 1 = Wired-OR SPSCK, MOSI, and MISO pins 0 = Normal push-pull SPSCK, MOSI, and MISO pins SPE -- SPI Enable This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. (See 21.9 Resetting the SPI.) Reset clears the SPE bit. 1 = SPI module enabled 0 = SPI module disabled SPTIE-- SPI Transmit Interrupt Enable This read/write bit enables CPU interrupt requests generated by the SPTE bit. SPTE is set when a byte transfers from the transmit data register to the shift register. Reset clears the SPTIE bit. 1 = SPTE CPU interrupt requests enabled 0 = SPTE CPU interrupt requests disabled 21.13.2 SPI Status and Control Register The SPI status and control register contains flags to signal these conditions: * * * * * * * Receive data register full Failure to clear SPRF bit before next byte is received (overflow error) Inconsistent logic level on SS pin (mode fault error) Transmit data register empty Enable error interrupts Enable mode fault error detection Select master SPI baud rate
The SPI status and control register also contains bits that perform these functions:
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Serial Peripheral Interface (SPI) Module I/O Registers
Address: $0011 Bit 7 Read: SPRF Write: Reset: 0
6 ERRIE
5 OVRF
4 MODF 0
3 SPTE 1
2 MODFEN 0
1 SPR1 0
Bit 0 SPR0 0
0 0 = Unimplemented
Figure 21-14. SPI Status and Control Register (SPSCR) SPRF -- SPI Receiver Full Bit This clearable, read-only flag is set each time a byte transfers from the shift register to the receive data register. SPRF generates a CPU interrupt request if the SPRIE bit in the SPI control register is set also. During an SPRF CPU interrupt, the CPU clears SPRF by reading the SPI status and control register with SPRF set and then reading the SPI data register. Reset clears the SPRF bit. 1 = Receive data register full 0 = Receive data register not full ERRIE -- Error Interrupt Enable Bit This read/write bit enables the MODF and OVRF bits to generate CPU interrupt requests. Reset clears the ERRIE bit. 1 = MODF and OVRF can generate CPU interrupt requests 0 = MODF and OVRF cannot generate CPU interrupt requests OVRF -- Overflow Bit This clearable, read-only flag is set if software does not read the byte in the receive data register before the next full byte enters the shift register. In an overflow condition, the byte already in the receive data register is unaffected, and the byte that shifted in last is lost. Clear the OVRF bit by reading the SPI status and control register with OVRF set and then reading the receive data register. Reset clears the OVRF bit. 1 = Overflow 0 = No overflow MODF -- Mode Fault Bit This clearable, read-only flag is set in a slave SPI if the SS pin goes high during a transmission with the MODFEN bit set. In a master SPI, the MODF flag is set if the SS pin goes low at any time with the MODFEN bit set. Clear the MODF bit by reading the SPI status and control register (SPSCR) with MODF set and then writing to the SPI control register (SPCR). Reset clears the MODF bit. 1 = SS pin at inappropriate logic level 0 = SS pin at appropriate logic level SPTE -- SPI Transmitter Empty Bit This clearable, read-only flag is set each time the transmit data register transfers a byte into the shift register. SPTE generates an SPTE CPU interrupt request or an SPTE DMA service request if the SPTIE bit in the SPI control register is set also.
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Serial Peripheral Interface (SPI) Module
NOTE: Do not write to the SPI data register unless the SPTE bit is high. During an SPTE CPU interrupt, the CPU clears the SPTE bit by writing to the transmit data register. Reset sets the SPTE bit. 1 = Transmit data register empty 0 = Transmit data register not empty MODFEN -- Mode Fault Enable Bit This read/write bit, when set to 1, allows the MODF flag to be set. If the MODF flag is set, clearing the MODFEN does not clear the MODF flag. If the SPI is enabled as a master and the MODFEN bit is low, then the SS pin is available as a general-purpose I/O. If the MODFEN bit is set, then this pin is not available as a general-purpose I/O. When the SPI is enabled as a slave, the SS pin is not available as a general-purpose I/O regardless of the value of MODFEN. See 21.12.4 SS (Slave Select). If the MODFEN bit is low, the level of the SS pin does not affect the operation of an enabled SPI configured as a master. For an enabled SPI configured as a slave, having MODFEN low only prevents the MODF flag from being set. It does not affect any other part of SPI operation. See 21.7.2 Mode Fault Error. SPR1 and SPR0 -- SPI Baud Rate Select Bits In master mode, these read/write bits select one of four baud rates as shown in Table 21-4. SPR1 and SPR0 have no effect in slave mode. Reset clears SPR1 and SPR0. Table 21-4. SPI Master Baud Rate Selection
SPR1 and SPR0 00 01 10 11 Baud Rate Divisor (BD) 2 8 32 128
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Use this formula to calculate the SPI baud rate: CGMOUT Baud rate = ------------------------2 x BD where: CGMOUT = base clock output of the clock generator module (CGM) BD = baud rate divisor
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Serial Peripheral Interface (SPI) Module I/O Registers
21.13.3 SPI Data Register The SPI data register consists of the read-only receive data register and the write-only transmit data register. Writing to the SPI data register writes data into the transmit data register. Reading the SPI data register reads data from the receive data register. The transmit data and receive data registers are separate registers that can contain different values. See Figure 21-2.
Address: $0012 Bit 7 Read: R7 T7 Write: Reset: 6 R6 T6 5 R5 T5 4 R4 T4 3 R3 T3 2 R2 T2 1 R1 T1 Bit 0 R0 T0
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Unaffected by reset
Figure 21-15. SPI Data Register (SPDR) R7-R0/T7-T0 -- Receive/Transmit Data Bits NOTE: Do not use read-modify-write instructions on the SPI data register since the register read is not the same as the register written.
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Data Sheet -- MC68HC908GZ8
Section 22. Timebase Module (TBM)
22.1 Introduction
This section describes the timebase module (TBM). The TBM will generate periodic interrupts at user selectable rates using a counter clocked by the external clock source. This TBM version uses 15 divider stages, eight of which are user selectable. A configuration option bit to select an additional 128 divide of the external clock source can be selected. See Section 8. Configuration Register (CONFIG)
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22.2 Features
Features of the TBM module include: * * * External clock or an additional divide-by-128 selected by configuration option bit as clock source Software configurable periodic interrupts with divide-by: 8, 16, 32, 64, 128, 2048, 8192, and 32768 taps of the selected clock source Configurable for operation during stop mode to allow periodic wakeup from stop
22.3 Functional Description
This module can generate a periodic interrupt by dividing the clock source supplied from the clock generator module, CGMXCLK. The counter is initialized to all 0s when TBON bit is cleared. The counter, shown in Figure 22-1, starts counting when the TBON bit is set. When the counter overflows at the tap selected by TBR2-TBR0, the TBIF bit gets set. If the TBIE bit is set, an interrupt request is sent to the CPU. The TBIF flag is cleared by writing a 1 to the TACK bit. The first time the TBIF flag is set after enabling the timebase module, the interrupt is generated at approximately half of the overflow period. Subsequent events occur at the exact period. The timebase module may remain active after execution of the STOP instruction if the crystal oscillator has been enabled to operate during stop mode through the OSCENINSTOP bit in the configuration register. The timebase module can be used in this mode to generate a periodic wakeup from stop mode.
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Timebase Module (TBM)
22.4 Interrupts
The timebase module can periodically interrupt the CPU with a rate defined by the selected TBMCLK and the select bits TBR2-TBR0. When the timebase counter chain rolls over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase interrupt, the counter chain overflow will generate a CPU interrupt request.
TBMCLKSEL FROM CONFIG2
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CGMXCLK FROM CGM MODULE
DIVIDE BY 128 PRESCALER
0 1
TBMCLK
TBON
/2
/2
/2
/2
/2
/2
/2
TBMINT
TBR2
/2
/2
/2
/2
/2
/2
/2
/2
TACK
TBR1
TBR0
TBIF 000 001 010 011 100 101 110 111 SEL R
TBIE
Figure 22-1. Timebase Block Diagram NOTE: Interrupts must be acknowledged by writing a logic 1 to the TACK bit.
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Timebase Module (TBM) TBM Interrupt Rate
22.5 TBM Interrupt Rate
The interrupt rate is determined by the equation: t TBMRATE 1 Divider = ------------------------------- = --------------------------f f TBMRATE TBMCLK
where: fTBMCLK =Frequency supplied from the clock generator (CGM) module Divider =Divider value as determined by TBR2-TBR0 settings, see Table 22-1 Table 22-1. Timebase Divider Selection
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Divider Tap TBR2 0 0 0 0 1 1 1 1 TBR1 0 0 1 1 0 0 1 1 TBR0 0 0 1 0 1 0 1 0 1 32,768 8192 2048 128 64 32 16 8 TMBCLKSEL 1 4,194,304 1,048,576 262144 16,384 8192 4096 2048 1024
As an example, a clock source of 4.9152 MHz, with the TMCLKSEL set for divide-by-128 and the TBR2-TBR0 set to {011}, the divider tap is1 and the interrupt rate calculates to: 1/(4.9152 x 106/128) = 26 s NOTE: Do not change TBR2-TBR0 bits while the timebase is enabled (TBON = 1).
22.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes. 22.6.1 Wait Mode The timebase module remains active after execution of the WAIT instruction. In wait mode the timebase register is not accessible by the CPU. If the timebase functions are not required during wait mode, reduce the power consumption by stopping the timebase before executing the WAIT instruction.
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Timebase Module (TBM)
22.6.2 Stop Mode The timebase module may remain active after execution of the STOP instruction if the internal clock generator has been enabled to operate during stop mode through the OSCENINSTOP bit in the configuration register. The timebase module can be used in this mode to generate a periodic wakeup from stop mode. If the internal clock generator has not been enabled to operate in stop mode, the timebase module will not be active during stop mode. In stop mode, the timebase register is not accessible by the CPU. If the timebase functions are not required during stop mode, reduce power consumption by disabling the timebase module before executing the STOP instruction.
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22.7 Timebase Control Register
The timebase has one register, the timebase control register (TBCR), which is used to enable the timebase interrupts and set the rate.
Address: $001C Bit 7 Read: Write: Reset: 0 TBIF 6 TBR2 0 5 TBR1 0 4 TBR0 0 3 0 TACK 0 R 2 TBIE 0 = Reserved 1 TBON 0 Bit 0 R 0
= Unimplemented
Figure 22-2. Timebase Control Register (TBCR) TBIF -- Timebase Interrupt Flag This read-only flag bit is set when the timebase counter has rolled over. 1 = Timebase interrupt pending 0 = Timebase interrupt not pending TBR2-TBR0 -- Timebase Divider Selection Bits These read/write bits select the tap in the counter to be used for timebase interrupts as shown in Table 22-1. NOTE: Do not change TBR2-TBR0 bits while the timebase is enabled (TBON = 1). TACK-- Timebase Acknowledge Bit The TACK bit is a write-only bit and always reads as 0. Writing a logic 1 to this bit clears TBIF, the timebase interrupt flag bit. Writing a logic 0 to this bit has no effect. 1 = Clear timebase interrupt flag 0 = No effect
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Timebase Module (TBM) Timebase Control Register
TBIE -- Timebase Interrupt Enabled Bit This read/write bit enables the timebase interrupt when the TBIF bit becomes set. Reset clears the TBIE bit. 1 = Timebase interrupt is enabled. 0 = Timebase interrupt is disabled. TBON -- Timebase Enabled Bit This read/write bit enables the timebase. Timebase may be turned off to reduce power consumption when its function is not necessary. The counter can be initialized by clearing and then setting this bit. Reset clears the TBON bit. 1 = Timebase is enabled. 0 = Timebase is disabled and the counter initialized to 0s.
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Timebase Module (TBM)
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Data Sheet 304 Timebase Module (TBM)
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Data Sheet -- MC68HC908GZ8
Section 23. Timer Interface Module (TIM)
23.1 Introduction
This section describes the timer interface (TIM) module. The TIM is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 23-1 is a block diagram of the TIM. This particular MCU has two timer interface modules which are denoted as TIM1 and TIM2.
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PRESCALER SELECT INTERNAL BUS CLOCK TSTOP TRST 16-BIT COUNTER 16-BIT COMPARATOR TMODH:TMODL TOV0 CHANNEL 0 16-BIT COMPARATOR TCH0H:TCH0L 16-BIT LATCH MS0A MS0B TOV1 INTERNAL BUS CHANNEL 1 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH MS1A CH1IE CH1F INTERRUPT LOGIC ELS1B ELS1A CH1MAX PORT LOGIC T[1,2]CH1 CH0IE CH0F INTERRUPT LOGIC ELS0B ELS0A CH0MAX PORT LOGIC T[1,2]CH0 PRESCALER
PS2
PS1
PS0
TOF TOIE
INTERRUPT LOGIC
Figure 23-1. TIM Block Diagram
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Timer Interface Module (TIM)
23.2 Features
Features of the TIM include: * Two input capture/output compare channels: - Rising-edge, falling-edge, or any-edge input capture trigger - Set, clear, or toggle output compare action Buffered and unbuffered pulse-width-modulation (PWM) signal generation Programmable TIM clock input with 7-frequency internal bus clock prescaler selection Free-running or modulo up-count operation Toggle any channel pin on overflow TIM counter stop and reset bits
* * *
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* *
23.3 Pin Name Conventions
The text that follows describes both timers, TIM1 and TIM2. The TIM input/output (I/O) pin names are T[1,2]CH0 (timer channel 0) and T[1,2]CH1 (timer channel 1), where "1" is used to indicate TIM1 and "2" is used to indicate TIM2. The two TIMs share four I/O pins with four port D I/O port pins. The full names of the TIM I/O pins are listed in Table 23-1. The generic pin names appear in the text that follows. Table 23-1. Pin Name Conventions
TIM Generic Pin Names: TIM1 Full TIM Pin Names: TIM2 PTD6/T2CH0 PTD7/T2CH1 T[1,2]CH0 PTD4/T1CH0 T[1,2]CH1 PTD5/T1CH1
NOTE:
References to either timer 1 or timer 2 may be made in the following text by omitting the timer number. For example, TCH0 may refer generically to T1CH0 and T2CH0, and TCH1 may refer to T1CH1 and T2CH1.
23.4 Functional Description
Figure 23-1 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing reference for the input capture and output compare functions. The TIM counter modulo registers, TMODH:TMODL, control the modulo value of the TIM counter. Software can read the TIM counter value at any time without affecting the counting sequence. The two TIM channels (per timer) are programmable independently as input capture or output compare channels. If a channel is configured as input capture,
Data Sheet 306 Timer Interface Module (TIM) MC68HC908GZ8 MOTOROLA
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Timer Interface Module (TIM) Functional Description
then an internal pullup device may be enabled for that channel. See 17.5.3 Port D Input Pullup Enable Register. Figure 23-2 summarizes the timer registers. NOTE: References to either timer 1 or timer 2 may be made in the following text by omitting the timer number. For example, TSC may generically refer to both T1SC and T2SC.
Bit 7 TOF 0 0 Bit 15 0 Bit 7 0 Bit 15 1 Bit 7 1 CH0F 0 0 Bit 15 6 TOIE 0 14 0 6 0 14 1 6 1 CH0IE 0 14 5 TSTOP 1 13 0 5 0 13 1 5 1 MS0B 0 13 4 0 TRST 0 12 0 4 0 12 1 4 1 MS0A 0 12 0 11 0 3 0 11 1 3 1 ELS0B 0 11 3 0 2 PS2 0 10 0 2 0 10 1 2 1 ELS0A 0 10 1 PS1 0 9 0 1 0 9 1 1 1 TOV0 0 9 Bit 0 PS0 0 Bit 8 0 Bit 0 0 Bit 8 1 Bit 0 1 CH0MAX 0 Bit 8
Addr. $0020
Register Name Timer 1 Status and Control Read: Register (T1SC) Write: See page 315. Reset: Timer 1 Counter Read: Register High (T1CNTH) Write: See page 317. Reset: Timer 1 Counter Read: Register Low (T1CNTL) Write: See page 317. Reset:
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$0021
$0022
Timer 1 Counter Modulo Reg- Read: $0023 ister High (T1MODH) Write: See page 317. Reset: $0024 Timer 1 Counter Modulo Read: Register Low (T1MODL) Write: See page 318. Reset:
Timer 1 Channel 0 Status and Read: $0025 Control Register (T1SC0) Write: See page 318. Reset: $0026 Timer 1 Channel 0 Read: Register High (T1CH0H) Write: See page 321. Reset: Timer 1 Channel 0 Read: Register Low (T1CH0L) Write: See page 321. Reset: Timer 1 Channel 1 Status and Read: Control Register (T1SC1) Write: See page 318. Reset: Timer 1 Channel 1 Read: Register High (T1CH1H) Write: See page 322. Reset:
Indeterminate after reset Bit 7 6 5 4 3 2 1 Bit 0
$0027
Indeterminate after reset CH1F 0 0 Bit 15 CH1IE 0 14 0 0 13 MS1A 0 12 ELS1B 0 11 ELS1A 0 10 TOV1 0 9 CH1MAX 0 Bit 8
$0028
$0029
Indeterminate after reset = Unimplemented
Figure 23-2. TIM I/O Register Summary (Sheet 1 of 2)
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Timer Interface Module (TIM)
Addr. $002A
Register Name Timer 1 Channel 1 Read: Register Low (T1CH1L) Write: See page 322. Reset: Timer 2 Status and Control Read: Register (T2SC) Write: See page 315. Reset: Timer 2 Counter Read: Register High (T2CNTH) Write: See page 317. Reset: Timer 2 Counter Read: Register Low (T2CNTL) Write: See page 317. Reset:
Bit 7 Bit 7
6 6
5 5
4 4
3 3
2 2
1 1
Bit 0 Bit 0
Indeterminate after reset TOF 0 0 Bit 15 0 Bit 7 0 Bit 15 1 Bit 7 1 CH0F 0 0 Bit 15 TOIE 0 14 0 6 0 14 1 6 1 CH0IE 0 14 TSTOP 1 13 0 5 0 13 1 5 1 MS0B 0 13 0 TRST 0 12 0 4 0 12 1 4 1 MS0A 0 12 0 11 0 3 0 11 1 3 1 ELS0B 0 11 0 PS2 0 10 0 2 0 10 1 2 1 ELS0A 0 10 PS1 0 9 0 1 0 9 1 1 1 TOV0 0 9 PS0 0 Bit 8 0 Bit 0 0 Bit 8 1 Bit 0 1 CH0MAX 0 Bit 8
$002B
$002C
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$002D
Timer 2 Counter Modulo Reg- Read: $002E ister High (T2MODH) Write: See page 317. Reset: $002F Timer 2 Counter Modulo Read: Register Low (T2MODL) Write: See page 318. Reset:
Timer 2 Channel 0 Status and Read: $0030 Control Register (T2SC0) Write: See page 318. Reset: $0031 Timer 2 Channel 0 Read: Register High (T2CH0H) Write: See page 321. Reset: Timer 2 Channel 0 Read: Register Low (T2CH0L) Write: See page 321. Reset: Timer 2 Channel 1 Status and Read: Control Register (T2SC1) Write: See page 318. Reset: Timer 2 Channel 1 Read: Register High (T2CH1H) Write: See page 322. Reset: Timer 2 Channel 1 Read: Register Low (T2CH1L) Write: See page 322. Reset:
Indeterminate after reset Bit 7 6 5 4 3 2 1 Bit 0
$0032
Indeterminate after reset CH1F 0 0 Bit 15 CH1IE 0 14 0 0 13 MS1A 0 12 ELS1B 0 11 ELS1A 0 10 TOV1 0 9 CH1MAX 0 Bit 8
$0033
$0034
Indeterminate after reset Bit 7 6 5 4 3 2 1 Bit 0
$0035
Indeterminate after reset = Unimplemented
Figure 23-2. TIM I/O Register Summary (Sheet 2 of 2)
Data Sheet 308 Timer Interface Module (TIM)
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Timer Interface Module (TIM) Functional Description
23.4.1 TIM Counter Prescaler The TIM clock source can be one of the seven prescaler outputs. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register select the TIM clock source. 23.4.2 Input Capture With the input capture function, the TIM can capture the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input captures can generate TIM CPU interrupt requests. 23.4.3 Output Compare With the output compare function, the TIM can generate a periodic pulse with a programmable polarity, duration, and frequency. When the counter reaches the value in the registers of an output compare channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU interrupt requests. 23.4.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in 23.4.3 Output Compare. The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. The TIM may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the output compare value on channel x: * When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value. When changing to a larger output compare value, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current counter overflow
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*
MC68HC908GZ8 MOTOROLA Timer Interface Module (TIM)
Data Sheet 309
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Timer Interface Module (TIM)
period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 23.4.3.2 Buffered Output Compare Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The output compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the output after the TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that control the output are the ones written to last. TSC0 controls and monitors the buffered output compare function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. NOTE: In buffered output compare operation, do not write new output compare values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered output compares.
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23.4.4 Pulse Width Modulation (PWM) By using the toggle-on-overflow feature with an output compare channel, the TIM can generate a PWM signal. The value in the TIM counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIM counter modulo registers. The time between overflows is the period of the PWM signal. As Figure 23-3 shows, the output compare value in the TIM channel registers determines the pulse width of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIM to clear the channel pin on output compare if the state of the PWM pulse is logic 1. Program the TIM to set the pin if the state of the PWM pulse is logic 0. The value in the TIM counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing $00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is $000. See 23.9.1 TIM Status and Control Register.
Data Sheet 310 Timer Interface Module (TIM)
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Timer Interface Module (TIM) Functional Description
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PULSE WIDTH TCHx
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OUTPUT COMPARE
OUTPUT COMPARE
OUTPUT COMPARE
Figure 23-3. PWM Period and Pulse Width The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers produces a duty cycle of 128/256 or 50%. 23.4.4.1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in 23.4.4 Pulse Width Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that PWM period. Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. The TIM may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x: * When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value. When changing to a longer pulse width, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same PWM period.
*
MC68HC908GZ8 MOTOROLA Timer Interface Module (TIM)
Data Sheet 311
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Timer Interface Module (TIM)
NOTE: In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value.
23.4.4.2 Buffered PWM Signal Generation Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the pulse width of the output.
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Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The TIM channel 0 registers initially control the pulse width on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIM channel registers (0 or 1) that control the pulse width are the ones written to last. TSC0 controls and monitors the buffered PWM function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. NOTE: In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered PWM signals.
23.4.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1. In the TIM status and control register (TSC): a. Stop the TIM counter by setting the TIM stop bit, TSTOP. b. Reset the TIM counter and prescaler by setting the TIM reset bit, TRST. 2. In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM period. 3. In the TIM channel x registers (TCHxH:TCHxL), write the value for the required pulse width. 4. In TIM channel x status and control register (TSCx): a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare or PWM signals) to the mode select bits, MSxB:MSxA. See Table 23-3. b. Write 1 to the toggle-on-overflow bit, TOVx.
Data Sheet 312 Timer Interface Module (TIM)
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Timer Interface Module (TIM) Interrupts
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. See Table 23-3. NOTE: In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. 5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP.
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Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0 (TSCR0) controls and monitors the PWM signal from the linked channels. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle output. Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty cycle output. See 23.9.4 TIM Channel Status and Control Registers.
23.5 Interrupts
The following TIM sources can generate interrupt requests: * TIM overflow flag (TOF) -- The TOF bit is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control register. TIM channel flags (CH1F:CH0F) -- The CHxF bit is set when an input capture or output compare occurs on channel x. Channel x TIM CPU interrupt requests are controlled by the channel x interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE = 1. CHxF and CHxIE are in the TIM channel x status and control register.
*
23.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes.
MC68HC908GZ8 MOTOROLA Timer Interface Module (TIM)
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Timer Interface Module (TIM)
23.6.1 Wait Mode The TIM remains active after the execution of a WAIT instruction. In wait mode, the TIM registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode. If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction. 23.6.2 Stop Mode The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect register conditions or the state of the TIM counter. TIM operation resumes when the MCU exits stop mode after an external interrupt.
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23.7 TIM During Break Interrupts
A break interrupt stops the TIM counter. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during the break state. See 20.7.3 Break Flag Control Register. To allow software to clear status bits during a break interrupt, write a logic 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state. To protect status bits during the break state, write a logic 0 to the BCFE bit. With BCFE at logic 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at logic 0. After the break, doing the second step clears the status bit.
23.8 I/O Signals
Port D shares four of its pins with the TIM. The four TIM channel I/O pins are T1CH0, T1CH1, T2CH0, and T2CH1 as described in 23.3 Pin Name Conventions. Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. T1CH0 and T2CH0 can be configured as buffered output compare or buffered PWM pins.
Data Sheet 314 Timer Interface Module (TIM)
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Timer Interface Module (TIM) I/O Registers
23.9 I/O Registers
NOTE: References to either timer 1 or timer 2 may be made in the following text by omitting the timer number. For example, TSC may generically refer to both T1SC AND T2SC. These I/O registers control and monitor operation of the TIM: * * * * TIM status and control register (TSC) TIM counter registers (TCNTH:TCNTL) TIM counter modulo registers (TMODH:TMODL) TIM channel status and control registers (TSC0 and TSC1) TIM channel registers (TCH0H:TCH0L, TCH1H:TCH1L)
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*
23.9.1 TIM Status and Control Register The TIM status and control register (TSC): * * * * * Enables TIM overflow interrupts Flags TIM overflows Stops the TIM counter Resets the TIM counter Prescales the TIM counter clock
Address: T1SC, $0020 and T2SC, $002B Bit 7 Read: Write: Reset: TOF 0 0 6 TOIE 0 = Unimplemented 5 TSTOP 1 4 0 TRST 0 0 3 0 2 PS2 0 1 PS1 0 Bit 0 PS0 0
Figure 23-4. TIM Status and Control Register (TSC) TOF -- TIM Overflow Flag Bit This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set and then writing a logic 0 to TOF. If another TIM overflow occurs before the clearing sequence is complete, then writing logic 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic 1 to TOF has no effect. 1 = TIM counter has reached modulo value 0 = TIM counter has not reached modulo value
MC68HC908GZ8 MOTOROLA Timer Interface Module (TIM)
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Timer Interface Module (TIM)
TOIE -- TIM Overflow Interrupt Enable Bit This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit. 1 = TIM overflow interrupts enabled 0 = TIM overflow interrupts disabled TSTOP -- TIM Stop Bit This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM counter until software clears the TSTOP bit. 1 = TIM counter stopped 0 = TIM counter active
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NOTE:
Do not set the TSTOP bit before entering wait mode if the TIM is required to exit wait mode. TRST -- TIM Reset Bit Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM counter is reset and always reads as logic 0. Reset clears the TRST bit. 1 = Prescaler and TIM counter cleared 0 = No effect
NOTE:
Setting the TSTOP and TRST bits simultaneously stops the TIM counter at a value of $0000. PS[2:0] -- Prescaler Select Bits These read/write bits select one of the seven prescaler outputs as the input to the TIM counter as Table 23-2 shows. Reset clears the PS[2:0] bits. Table 23-2. Prescaler Selection
PS2 0 0 0 0 1 1 1 1 PS1 0 0 1 1 0 0 1 1 PS0 0 1 0 1 0 1 0 1 TIM Clock Source Internal bus clock / 1 Internal bus clock / 2 Internal bus clock / 4 Internal bus clock / 8 Internal bus clock / 16 Internal bus clock / 32 Internal bus clock / 64 Not available
Data Sheet 316 Timer Interface Module (TIM)
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Timer Interface Module (TIM) I/O Registers
23.9.2 TIM Counter Registers The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers. NOTE: If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL retains the value latched during the break.
Address: T1CNTH, $0021 and T2CNTH, $002C Bit 7 Read: Write: Reset: 0 0 = Unimplemented 0 0 0 0 0 0 Bit 15 6 14 5 13 4 12 3 11 2 10 1 9 Bit 0 Bit 8
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Figure 23-5. TIM Counter Registers High (TCNTH)
Address: T1CNTL, $0022 and T2CNTL, $002D Bit 7 Read: Write: Reset: 0 0 = Unimplemented 0 0 0 0 0 0 Bit 7 6 6 5 5 4 4 3 3 2 2 1 1 Bit 0 Bit 0
Figure 23-6. TIM Counter Registers Low (TCNTL) 23.9.3 TIM Counter Modulo Registers The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.
Address: T1MODH, $0023 and T2MODH, $002E Bit 7 Read: Write: Reset: Bit 15 1 6 14 1 5 13 1 4 12 1 3 11 1 2 10 1 1 9 1 Bit 0 Bit 8 1
Figure 23-7. TIM Counter Modulo Register High (TMODH)
MC68HC908GZ8 MOTOROLA Timer Interface Module (TIM)
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Timer Interface Module (TIM)
Address: T1MODL, $0024 and T2MODL, $002F Bit 7 Read: Write: Reset: Bit 7 1 6 6 1 5 5 1 4 4 1 3 3 1 2 2 1 1 1 1 Bit 0 Bit 0 1
Figure 23-8. TIM Counter Modulo Register Low (TMODL) NOTE: Reset the TIM counter before writing to the TIM counter modulo registers.
23.9.4 TIM Channel Status and Control Registers
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Each of the TIM channel status and control registers: * * * * * * * * Flags input captures and output compares Enables input capture and output compare interrupts Selects input capture, output compare, or PWM operation Selects high, low, or toggling output on output compare Selects rising edge, falling edge, or any edge as the active input capture trigger Selects output toggling on TIM overflow Selects 0% and 100% PWM duty cycle Selects buffered or unbuffered output compare/PWM operation
Address: T1SC0, $0025 and T2SC0, $0030 Bit 7 Read: Write: Reset: CH0F 0 0 6 CH0IE 0 5 MS0B 0 4 MS0A 0 3 ELS0B 0 2 ELS0A 0 1 TOV0 0 Bit 0 CH0MAX 0
Figure 23-9. TIM Channel 0 Status and Control Register (TSC0)
Address: T1SC1, $0028 and T2SC1, $0033 Bit 7 Read: Write: Reset: CH1F 0 0 6 CH1IE 0 5 0 0 4 MS1A 0 3 ELS1B 0 2 ELS1A 0 1 TOV1 0 Bit 0 CH1MAX 0
Figure 23-10. TIM Channel 1 Status and Control Register (TSC1) CHxF -- Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIM counter registers matches the value in the TIM channel x registers.
Data Sheet 318 Timer Interface Module (TIM) MC68HC908GZ8 MOTOROLA
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Timer Interface Module (TIM) I/O Registers
When TIM CPU interrupt requests are enabled (CHxIE = 1), clear CHxF by reading TIM channel x status and control register with CHxF set and then writing a logic 0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing logic 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect. 1 = Input capture or output compare on channel x 0 = No input capture or output compare on channel x CHxIE -- Channel x Interrupt Enable Bit This read/write bit enables TIM CPU interrupt service requests on channel x. Reset clears the CHxIE bit. 1 = Channel x CPU interrupt requests enabled 0 = Channel x CPU interrupt requests disabled MSxB -- Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM1 channel 0 and TIM2 channel 0 status and control registers. Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose I/O. Reset clears the MSxB bit. 1 = Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled MSxA -- Mode Select Bit A When ELSxB:A 00, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See Table 23-3. 1 = Unbuffered output compare/PWM operation 0 = Input capture operation When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin. See Table 23-3. Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high NOTE: Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIM status and control register (TSC). ELSxB and ELSxA -- Edge/Level Select Bits When channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to port D, and pin PTDx/TCHx is available as a general-purpose I/O pin. Table 23-3 shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits.
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MC68HC908GZ8 MOTOROLA Timer Interface Module (TIM)
Data Sheet 319
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Timer Interface Module (TIM)
Table 23-3. Mode, Edge, and Level Selection
MSxB:MSxA X0 X1 00 00 00 ELSxB:ELSxA 00 Output preset 00 01 10 11 01 10 11 01 10 11 Buffered output compare or buffered PWM Output compare or PWM Input capture Mode Configuration Pin under port control; initial output level high Pin under port control; initial output level low Capture on rising edge only Capture on falling edge only Capture on rising or falling edge Toggle output on compare Clear output on compare Set output on compare Toggle output on compare Clear output on compare Set output on compare
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01 01 01 1X 1X 1X
NOTE:
Before enabling a TIM channel register for input capture operation, make sure that the PTD/TCHx pin is stable for at least two bus clocks. TOVx -- Toggle On Overflow Bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no effect. Reset clears the TOVx bit. 1 = Channel x pin toggles on TIM counter overflow. 0 = Channel x pin does not toggle on TIM counter overflow.
NOTE:
When TOVx is set, a TIM counter overflow takes precedence over a channel x output compare if both occur at the same time. CHxMAX -- Channel x Maximum Duty Cycle Bit When the TOVx bit is at logic 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 23-11 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
Data Sheet 320 Timer Interface Module (TIM)
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Timer Interface Module (TIM) I/O Registers
OVERFLOW PERIOD TCHx
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
OUTPUT COMPARE CHxMAX
OUTPUT COMPARE
OUTPUT COMPARE
OUTPUT COMPARE
Figure 23-11. CHxMAX Latency
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23.9.5 TIM Channel Registers These read/write registers contain the captured TIM counter value of the input capture function or the output compare value of the output compare function. The state of the TIM channel registers after reset is unknown. In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is read. In output compare mode (MSxB:MSxA 0:0), writing to the high byte of the TIM channel x registers (TCHxH) inhibits output compares until the low byte (TCHxL) is written.
Address: T1CH0H, $0026 and T2CH0H, $0031 Bit 7 Read: Write: Reset: Bit 15 6 14 5 13 4 12 3 11 2 10 1 9 Bit 0 Bit 8
Indeterminate after reset
Figure 23-12. TIM Channel 0 Register High (TCH0H)
Address: T1CH0L, $0027 and T2CH0L $0032 Bit 7 Read: Write: Reset: Bit 7 6 6 5 5 4 4 3 3 2 2 1 1 Bit 0 Bit 0
Indeterminate after reset
Figure 23-13. TIM Channel 0 Register Low (TCH0L)
MC68HC908GZ8 MOTOROLA Timer Interface Module (TIM)
Data Sheet 321
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Timer Interface Module (TIM)
Address: T1CH1H, $0029 and T2CH1H, $0034 Bit 7 Read: Write: Reset: Bit 15 6 14 5 13 4 12 3 11 2 10 1 9 Bit 0 Bit 8
Indeterminate after reset
Figure 23-14. TIM Channel 1 Register High (TCH1H)
Address: T1CH1L, $002A and T2CH1L, $0035 Bit 7 6 6 5 5 4 4 3 3 2 2 1 1 Bit 0 Bit 0 Read: Write: Reset:
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Bit 7
Indeterminate after reset
Figure 23-15. TIM Channel 1 Register Low (TCH1L)
Data Sheet 322 Timer Interface Module (TIM)
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Data Sheet -- MC68HC908GZ8
Section 24. Electrical Specifications
24.1 Introduction
This section contains electrical and timing specifications.
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24.2 Absolute Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. NOTE: This device is not guaranteed to operate properly at the maximum ratings. Refer to 24.5 5-Vdc Electrical Characteristics and 24.6 3.3-Vdc Electrical Characteristics for guaranteed operating conditions.
Characteristic(1) Supply voltage Input voltage Maximum current per pin excluding those specified below Maximum current for pins PTC0-PTC4 Maximum current into VDD Maximum current out of VSS Storage temperature 1. Voltages referenced to VSS Symbol VDD VIn I IPTC0-PTC4 Imvdd Imvss Tstg Value -0.3 to + 6.0 VSS - 0.3 to VDD + 0.3 15 25 150 150 -55 to +150 Unit V V mA mA mA mA C
NOTE:
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. For proper operation, it is recommended that VIn and VOut be constrained to the range VSS (VIn or VOut) VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either VSS or VDD).
MC68HC908GZ8 MOTOROLA Electrical Specifications
Data Sheet 323
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Electrical Specifications
24.3 Functional Operating Range
Characteristic Operating temperature range Operating voltage range Symbol TA VDD Value -40 to +125 5.0 10% 3.3 10% Unit C V
24.4 Thermal Characteristics
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Characteristic Thermal resistance 32-pin LQFP 48-pin LQFP I/O pin power dissipation Power dissipation(1) Constant(2) Average junction temperature
Symbol JA PI/O PD
Value 95 95 User determined PD = (IDD x VDD) + PI/O = K/(TJ + 273 C) PD x (TA + 273 C) + PD2 x JA TA + (PD x JA)
Unit C/W W W
K TJ
W/C C
1. Power dissipation is a function of temperature. 2. K is a constant unique to the device. K can be determined for a known TA and measured PD. With this value of K, PD and TJ can be determined for any value of TA.
Data Sheet 324 Electrical Specifications
MC68HC908GZ8 MOTOROLA
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Freescale Semiconductor, Inc.
Electrical Specifications 5-Vdc Electrical Characteristics
24.5 5-Vdc Electrical Characteristics
Characteristic(1) Output high voltage (ILoad = -2.0 mA) all I/O pins (ILoad = -10.0 mA) all I/O pins (ILoad = -20.0 mA) pins PTC0-PTC4 only Maximum combined IOH for port PTA7-PTA3, port PTC0-PTC1, port E, port PTD0-PTD3 Maximum combined IOH for port PTA2-PTA0, port B, port PTC2-PTC6, port PTD4-PTD7 Maximum total IOH for all port pins Output low voltage (ILoad = 1.6 mA) all I/O pins (ILoad = 10 mA) all I/O pins (ILoad = 20mA) pins PTC0-PTC4 only Maximum combined IOH for port PTA7-PTA3, port PTC0-PTC1, port E, port PTD0-PTD3 Maximum combined IOH for port PTA2-PTA0, port B, port PTC2-PTC6, port PTD4-PTD7 Maximum total IOL for all port pins Input high voltage All ports, IRQ, RST, OSC1 Input low voltage All ports, IRQ, RST, OSC1 VDD supply current Run(3) Wait(4) Stop(5) 25C 25C with TBM enabled(6) 25C with LVI and TBM enabled(6) -40C to 125C with TBM enabled(6) -40C to 125C with LVI and TBM enabled(6) I/O ports Hi-Z leakage current(7) Input current Pullup resistors (as input only) Ports PTA7/KBD7-PTA0/KBD0, PTD7/T2CH1-PTD0/SS PTC6-PTC0/CANTX, -- -- IDD 20 6 30 12 mA mA A A A A A A A k Symbol Min Typ(2) -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- 50 50 100 0.4 1.5 1.5 50 50 100 VDD 0.2 x VDD Unit V V V mA mA mA V V V mA mA mA V V
VOH VOH VOH IOH1 IOH2 IOHT VOL VOL VOL IOL1 IOL2 IOLT VIH VIL
VDD - 0.8 VDD - 1.5 VDD - 1.5 -- -- --
Freescale Semiconductor, Inc...
-- -- -- -- -- -- 0.7 x VDD VSS
-- -- -- -- -- -10 --1 20
3 20 300 50 500 -- -- 45
-- -- -- -- -- +10 +1 65
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MC68HC908GZ8 MOTOROLA Electrical Specifications
Data Sheet 325
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Freescale Semiconductor, Inc.
Electrical Specifications
Characteristic(1) Capacitance Ports (as input or output) Monitor mode entry voltage Low-voltage inhibit, trip falling voltage Low-voltage inhibit, trip rising voltage Low-voltage inhibit reset/recover hysteresis (VTRIPF + VHYS = VTRIPR)
Symbol COut CIn VTST VTRIPF VTRIPR VHYS VPOR VPORRST RPOR
Min -- -- VDD + 2.5 3.90 4.20 -- 0 0 0.035
Typ(2) -- -- -- 4.25 4.35 100 -- 700 --
Max 12 8 VDD + 4.0 4.50 4.60 -- 100 800 --
Unit pF V V V mV mV mV V/ms
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POR rearm voltage(8) POR reset voltage(9) POR rise time ramp rate(10)
1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = TA (min) to TA (max), unless otherwise noted 2. Typical values reflect average measurements at midpoint of voltage range, 25C only. 3. Run (operating) IDD measured using external square wave clock source (fOSC = 32 MHz). All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules enabled. 4. Wait IDD measured using external square wave clock source (fOSC = 32 MHz). All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD. Measured with ICG and LVI enabled. 5. Stop IDD is measured with OSC1 = VSS. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. All ports configured as inputs. Typical values at midpoint of voltage range, 25C only. 6. Stop IDD with TBM enabled is measured using an external square wave clock source (fOSC = 32 MHz). All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. All inputs configured as inputs. 7. Pullups and pulldowns are disabled. Port B leakage is specified in 24.10 5.0-Volt ADC Characteristics. 8. Maximum is highest voltage that POR is guaranteed. 9. Maximum is highest voltage that POR is possible. 10. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached.
Data Sheet 326 Electrical Specifications
MC68HC908GZ8 MOTOROLA
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Freescale Semiconductor, Inc.
Electrical Specifications 3.3-Vdc Electrical Characteristics
24.6 3.3-Vdc Electrical Characteristics
Characteristic(1) Output high voltage (ILoad = -0.6 mA) all I/O pins (ILoad = -4.0 mA) all I/O pins (ILoad = -10.0 mA) pins PTC0-PTC4 only Maximum combined IOH for port PTA7-PTA3, port PTC0-PTC1, port E, port PTD0-PTD3 Maximum combined IOH for port PTA2-PTA0, port B, port PTC2-PTC6, port PTD4-PTD7 Maximum total IOH for all port pins Output low voltage (ILoad = 1.6 mA) all I/O pins (ILoad = 10 mA) all I/O pins (ILoad = 20 mA) pins PTC0-PTC4 only Maximum combined IOH for port PTA7-PTA3, port PTC0-PTC1, port E, port PTD0-PTD3 Maximum combined IOH for port PTA2-PTA0, port B, port PTC2-PTC6, port PTD4-PTD7 Maximum total IOL for all port pins Input high voltage All ports, IRQ, RST, OSC1 Input low voltage All ports, IRQ, RST, OSC1 VDD supply current Run(3) Wait(4) Stop(5) 25C 25C with TBM enabled(6) 25C with LVI and TBM enabled(6) -40C to 125C with TBM enabled(6) -40C to 125C with LVI and TBM enabled(6) I/O ports Hi-Z leakage current(7) Input current Pullup resistors (as input only) Ports PTA7/KBD7-PTA0/KBD0, PTC6-PTC0, PTD7/T2CH1-PTD0/SS -- -- IDD 8 3 12 6 mA mA A A A A A A A k Symbol Min Typ(2) -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- 30 30 60 0.3 1.0 0.8 30 30 60 VDD 0.3 x VDD Unit V V V mA mA mA V V V mA mA mA V V
VOH VOH VOH IOH1 IOH2 IOHT VOL VOL VOL IOL1 IOL2 IOLT VIH VIL
VDD - 0.3 VDD - 1.0 VDD - 1.0 -- -- --
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-- -- -- -- -- -- 0.7 x VDD VSS
-- -- -- -- -- -10 --1 20
2 12 200 30 300 -- -- 45
-- -- -- -- -- +10 +1 65
IIL IIn RPU
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MC68HC908GZ8 MOTOROLA Electrical Specifications
Data Sheet 327
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Freescale Semiconductor, Inc.
Electrical Specifications
Characteristic(1) Capacitance Ports (as input or output) Monitor mode entry voltage Low-voltage inhibit, trip falling voltage Low-voltage inhibit, trip rising voltage Low-voltage inhibit reset/recover hysteresis (VTRIPF + VHYS = VTRIPR)
Symbol COut CIn VTST VTRIPF VTRIPR VHYS VPOR VPORRST RPOR
Min -- -- VDD + 2.5 2.35 2.4 -- 0 0 0.02
Typ(2) -- -- -- 2.6 2.66 100 -- 700 --
Max 12 8 VDD + 4.0 2.7 2.8 -- 100 800 --
Unit pF V V V mV mV mV V/ms
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POR rearm voltage(8) POR reset voltage(9) POR rise time ramp rate(10)
1. VDD = 3.3 Vdc 10%, VSS = 0 Vdc, TA = TA (min) to TA (max), unless otherwise noted 2. Typical values reflect average measurements at midpoint of voltage range, 25C only. 3. Run (operating) IDD measured using external square wave clock source (fOSC = 16 MHz). All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. Measured with all modules enabled. 4. Wait IDD measured using external square wave clock source (fOSC = 16 MHz). All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD. Measured with ICG and LVI enabled. 5. Stop IDD is measured with OSC1 = VSS. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. All ports configured as inputs. Typical values at midpoint of voltage range, 25C only. 6. Stop IDD with TBM enabled is measured using an external square wave clock source (fOSC = 16 MHz). All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. All inputs configured as inputs. 7. Pullups and pulldowns are disabled. 8. Maximum is highest voltage that POR is guaranteed. 9. Maximum is highest voltage that POR is possible. 10. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached.
Data Sheet 328 Electrical Specifications
MC68HC908GZ8 MOTOROLA
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Freescale Semiconductor, Inc.
Electrical Specifications 5.0-Volt Control Timing
24.7 5.0-Volt Control Timing
Characteristic(1) Frequency of operation Crystal option External clock option
(2)
Symbol
Min
Max
Unit
fOSC fOP (fBus) tCYC tRL tILIH tILIL
1 dc -- 125 50 50 Note(3)
8 32 8 -- -- -- --
MHz
Internal operating frequency Internal clock period (1/fOP) RST input pulse width low
MHz ns ns ns tCYC
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IRQ interrupt pulse width low (edge-triggered) IRQ interrupt pulse period
1. VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VDD unless otherwise noted. 2. No more than 10% duty cycle deviation from 50%. 3. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tCYC.
24.8 3.3-Volt Control Timing
Characteristic(1) Frequency of operation Crystal option External clock option
(2)
Symbol
Min
Max
Unit
fOSC fOP (fBus) tCYC tRL tILIH tILIL
1 dc -- 250 125 125 Note(3)
8 16 4 -- -- -- --
MHz MHz ns ns ns tCYC
Internal operating frequency Internal clock period (1/fOP) RST input pulse width low IRQ interrupt pulse width low (edge-triggered) IRQ interrupt pulse period
1. VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VDD unless otherwise noted. 2. No more than 10% duty cycle deviation from 50%. 3. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tCYC.
tRL RST tILIL tILIH IRQ
Figure 24-1. RST and IRQ Timing
MC68HC908GZ8 MOTOROLA Electrical Specifications Data Sheet 329
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Freescale Semiconductor, Inc.
Electrical Specifications
24.9 Clock Generation Module Characteristics
24.9.1 CGM Component Specifications
Characteristic Crystal frequency Crystal load capacitance(1) Crystal fixed capacitance Crystal tuning capacitance Symbol fXCLK CL C1 C2 RB Min 1 -- -- -- 1 Typ 4 -- (2 x CL) -5 (2 x CL) -5 10 Max 8 -- -- -- 20 Unit MHz pF pF pF M
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Feedback bias resistor 1. Consult crystal manufacturer's data.
24.9.2 CGM Electrical Specifications
Characteristic Reference frequency (for PLL operation) Range nominal multiplier Programmed VCO center-of-range frequency(1) Symbol fRCLK fNOM fVRS Min 1 -- -- Typ 4 71.42 (Lx2E)fNOM Max 8 -- -- Unit MHz KHz MHz
1. See 7.3.6 Programming the PLL for detailed instruction on selecting appropriate values for L and E.
Data Sheet 330 Electrical Specifications
MC68HC908GZ8 MOTOROLA
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Freescale Semiconductor, Inc.
Electrical Specifications 5.0-Volt ADC Characteristics
24.10 5.0-Volt ADC Characteristics
Characteristic(1) Supply voltage Input voltages Resolution Absolute accuracy Symbol VDDAD VADIN BAD AAD fADIC RAD tADPU tADC tADS MAD ZADI FADI CADI IVREF AAD -- 000 3FC -- -- -1 -1/8 003 3FF 30 1.6 +1 +7/8 Min Max Unit Comments VDDAD should be tied to the same potential as VDD via separate traces. VADIN <= VDDAD
4.5 0 10 -4 500 k VSSAD 16 16 5
5.5 VDDAD 10 +4 1.048 M VDDAD -- 17 --
V V Bits Counts Hz V tAIC cycles tAIC cycles tAIC cycles Guaranteed Hex Hex pF mA LSB LSB
Includes quantization tAIC = 1/fADIC
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ADC internal clock Conversion range Power-up time Conversion time Sample time Monotonicity Zero input reading Full-scale reading Input capacitance VDDAD/VREFH current Absolute accuracy (8-bit truncation mode) Quantization error (8-bit truncation mode)
VADIN = VSSA VADIN = VDDA Not tested
Includes quantization
1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, VDDAD/VREFH = 5.0 Vdc 10%, VSSAD/VREFL = 0 Vdc
MC68HC908GZ8 MOTOROLA Electrical Specifications
Data Sheet 331
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Freescale Semiconductor, Inc.
Electrical Specifications
24.11 3.3-Volt ADC Characteristics
Characteristic(1) Supply voltage Input voltages Resolution Absolute accuracy Symbol VDDAD VADIN BAD AAD fADIC RAD tADPU tADC tADS MAD ZADI FADI CADI IVREF AAD -- 000 3FA -- -- -1 -1/8 005 3FF 30 1.2 +1 +7/8 Min Max Unit Comments VDDAD should be tied to the same potential as VDD via separate traces. VADIN <= VDDAD
3.0 0 10 -6 500 k VSSAD 16 16 5
3.6 VDDAD 10 +6 1.048 M VDDAD -- 17 --
V V Bits Counts Hz V tAIC cycles tAIC cycles tAIC cycles Guaranteed Hex Hex pF mA LSB LSB
Includes quantization tAIC = 1/fADIC
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ADC internal clock Conversion range Power-up time Conversion time Sample time Monotonicity Zero input reading Full-scale reading Input capacitance VDDAD/VREFH current Absolute accuracy (8-bit truncation mode) Quantization error (8-bit truncation mode)
VADIN = VSSA VADIN = VDDA Not tested
Includes quantization
1. VDD = 3.3 Vdc 10%, VSS = 0 Vdc, VDDAD/VREFH = 3.3 Vdc 10%, VSSAD/VREFL = 0 Vdc
Data Sheet 332 Electrical Specifications
MC68HC908GZ8 MOTOROLA
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Freescale Semiconductor, Inc.
Electrical Specifications 5.0-Volt SPI Characteristics
24.12 5.0-Volt SPI Characteristics
Diagram Number(1) Characteristic(2) Operating frequency Master Slave Cycle time Master Slave Enable lead time Enable lag time Clock (SPSCK) high time Master Slave Clock (SPSCK) low time Master Slave Data setup time (inputs) Master Slave Data hold time (inputs) Master Slave Access time, slave(3) CPHA = 0 CPHA = 1 Disable time, slave(4) Data valid time, after enable edge Master Slave(5) Data hold time, outputs, after enable edge Master Slave Symbol Min Max Unit
fOP(M) fOP(S) tCYC(M) tCYC(S) tLead(S) tLag(S) tSCKH(M) tSCKH(S) tSCKL(M) tSCKL(S) tSU(M) tSU(S) tH(M) tH(S) tA(CP0) tA(CP1) tDIS(S) tV(M) tV(S) tHO(M) tHO(S)
fOP/128 dc 2 1 1 1 tCYC -25 1/2 tCYC -25 tCYC -25 1/2 tCYC -25 30 30
fOP/2 fOP 128 -- -- -- 64 tCYC -- 64 tCYC -- -- --
MHz MHz tCYC tCYC tCYC tCYC ns ns
1 2 3 4
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5
ns ns
6
ns ns
7
30 30
-- --
ns ns
8
0 0 --
40 40 40
ns ns ns
9
10
-- --
50 50
ns ns
11
0 0
-- --
ns ns
1. Numbers refer to dimensions in Figure 24-2 and Figure 24-3. 2. All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. 3. Time to data active from high-impedance state 4. Hold time to high-impedance state 5. With 100 pF on all SPI pins
MC68HC908GZ8 MOTOROLA Electrical Specifications
Data Sheet 333
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Electrical Specifications
24.13 3.3-Volt SPI Characteristics
Diagram Number(1) Characteristic(2) Operating frequency Master Slave Cycle time Master Slave Enable lead time Enable lag time Clock (SPSCK) high time Master Slave Clock (SPSCK) low time Master Slave Data setup time (inputs) Master Slave Data hold time (inputs) Master Slave Access time, slave(3) CPHA = 0 CPHA = 1 Disable time, slave(4) Data valid time, after enable edge Master Slave(5) Data hold time, outputs, after enable edge Master Slave Symbol Min Max Unit
fOP(M) fOP(S) tCYC(M) tCYC(S) tLead(S) tLag(S) tSCKH(M) tSCKH(S) tSCKL(M) tSCKL(S) tSU(M) tSU(S) tH(M) tH(S) tA(CP0) tA(CP1) tDIS(S) tV(M) tV(S) tHO(M) tHO(S)
fOP/128 DC 2 1 1 1 tcyc -35 1/2 tcyc -35 tcyc -35 1/2 tcyc -35 40 40
fOP/2 fOP 128 -- -- -- 64 tcyc -- 64 tcyc -- -- --
MHz MHz tcyc tcyc tcyc tcyc ns ns
1 2 3 4
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5
ns ns
6
ns ns
7
40 40
-- --
ns ns
8
0 0 --
50 50 50
ns ns ns
9
10
-- --
60 60
ns ns
11
0 0
-- --
ns ns
1. Numbers refer to dimensions in Figure 24-2 and Figure 24-3. 2. All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. 3. Time to data active from high-impedance state 4. Hold time to high-impedance state 5. With 100 pF on all SPI pins
Data Sheet 334 Electrical Specifications
MC68HC908GZ8 MOTOROLA
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Electrical Specifications 3.3-Volt SPI Characteristics
SS INPUT
SS PIN OF MASTER HELD HIGH 1
SPSCK OUTPUT CPOL = 0
NOTE
5 4
SPSCK OUTPUT CPOL = 1
NOTE
5 4 6 7 LSB IN 10 BITS 6-1 11 MASTER LSB OUT
MISO INPUT
MSB IN 11
BITS 6-1
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MOSI OUTPUT
MASTER MSB OUT
Note: This first clock edge is generated internally, but is not seen at the SPSCK pin.
a) SPI Master Timing (CPHA = 0)
SS INPUT
SS PIN OF MASTER HELD HIGH 1
SPSCK OUTPUT CPOL = 0
5 4
NOTE
SPSCK OUTPUT CPOL = 1
5 4 6 7 LSB IN 10 BITS 6-1 MASTER LSB OUT
NOTE
MISO INPUT 10 MOSI OUTPUT
MSB IN 11 MASTER MSB OUT
BITS 6-1
Note: This last clock edge is generated internally, but is not seen at the SPSCK pin.
b) SPI Master Timing (CPHA = 1)
Figure 24-2. SPI Master Timing
MC68HC908GZ8 MOTOROLA Electrical Specifications
Data Sheet 335
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Electrical Specifications
SS INPUT 1 SPSCK INPUT CPOL = 0 2 SPSCK INPUT CPOL = 1 8 MISO INPUT SLAVE 6 MOSI OUTPUT MSB IN MSB OUT 7 10 BITS 6-1 BITS 6-1 11 LSB IN SLAVE LSB OUT 11 5 4 9 NOTE 5 4 3
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Note: Not defined but normally MSB of character just received
a) SPI Slave Timing (CPHA = 0)
SS INPUT 1 SPSCK INPUT CPOL = 0 2 SPSCK INPUT CPOL = 1 8 MISO OUTPUT 5 4 10 NOTE SLAVE 6 MOSI INPUT MSB IN MSB OUT 7 10 BITS 6-1 BITS 6-1 11 LSB IN 9 SLAVE LSB OUT 5 4 3
Note: Not defined but normally LSB of character previously transmitted
b) SPI Slave Timing (CPHA = 1)
Figure 24-3. SPI Slave Timing
Data Sheet 336 Electrical Specifications
MC68HC908GZ8 MOTOROLA
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Electrical Specifications Timer Interface Module Characteristics
24.14 Timer Interface Module Characteristics
Characteristic Timer input capture pulse width Timer Input capture period Symbol tTH, tTL tTLTL Min 2 Note
(1)
Max -- --
Unit tCYC tCYC
1. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tCYC.
tTLTL tTH
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INPUT CAPTURE RISING EDGE
tTLTL tTL INPUT CAPTURE FALLING EDGE
tTLTL tTH INPUT CAPTURE BOTH EDGES tTL
Figure 24-4. Input Capture Timing
MC68HC908GZ8 MOTOROLA Electrical Specifications
Data Sheet 337
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Freescale Semiconductor, Inc.
Electrical Specifications
24.15 Memory Characteristics
Characteristic RAM data retention voltage FLASH program bus clock frequency FLASH read bus clock frequency FLASH page erase time < 1K cycles > 1K cycles FLASH mass erase time Symbol VRDR -- fRead(1) tErase tMErase tnvs tnvh tnvhl tpgs tPROG trcv(2) tHV(3) -- -- Min 1.3 1 dc 1 4 4 10 5 100 5 30 1 -- 10k 10 Max -- -- 8M -- -- -- -- -- -- -- 40 -- 4 -- -- Unit V MHz Hz ms ms s s s s s s ms Cycles Years
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FLASH PGM/ERASE to HVEN set up time FLASH high-voltage hold time FLASH high-voltage hold time (mass erase) FLASH program hold time FLASH program time FLASH return to read time FLASH cumulative program HV period FLASH endurance FLASH data retention time
1. fRead is defined as the frequency range for which the FLASH memory can be read. 2. trcv is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump, by clearing HVEN to logic 0. 3. tHV is defined as the cumulative high voltage programming time to the same row before next erase. tHV must satisfy this condition: tnvs + tnvh + tpgs + (tPROG x 64) tHV max.
Data Sheet 338 Electrical Specifications
MC68HC908GZ8 MOTOROLA
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Data Sheet -- MC68HC908GZ8
Section 25. Ordering Information and Mechanical Specifications
25.1 Introduction
This section provides ordering information for the MC68HC908GZ8 along with the dimensions for:
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* *
32-pin low-profile quad flat pack (case 873A) 48-pin low-profile quad flat pack (case 932-03)
The following figures show the latest package drawings at the time of this publication. To make sure that you have the latest package specifications, contact your local Motorola Sales Office.
25.2 MC Order Numbers
Table 25-1. MC Order Numbers
MC Order Number MC68HC908GZ8CFJ MC68HC908GZ8VFJ MC68HC908GZ8MFJ MC68HC908GZ8CFA MC68HC908GZ8VFA MC68HC908GZ8MFA Temperature designators: C = -40C to +85C V = -40C to +105C M = -40C to +125C Operating Temperature Range -40C to +85C -40C to +105C -40C to +125C -40C to +85C -40C to +105C -40C to +125C Package
32-pin low-profile quad flat pack (LQFP)
48-pin low-profile quad flat pack (LQFP)
MC68HC908GZ8 MOTOROLA Ordering Information and Mechanical Specifications
Data Sheet 339
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Freescale Semiconductor, Inc.
Ordering Information and Mechanical Specifications
25.3 32-Pin Low-Profile Quad Flat Pack (LQFP)
-T-, -U-, -Z- AE P B1 DETAIL Y
8 17
A A1
32 25
4X
0.20 (0.008) AB T-U Z
1
-T- B
-U- V V1 AE
9
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DETAIL Y -Z-
4X
9
S1 S
0.20 (0.008) AC T-U Z
G -AB-
SEATING PLANE
DETAIL AD
-AC-
BASE METAL
N
F
8X
D
M_ R
0.20 (0.008)
M
AC T-U Z
0.10 (0.004) AC
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
CE
SECTION AE-AE
X DETAIL AD
Data Sheet 340 Ordering Information and Mechanical Specifications
GAUGE PLANE
0.250 (0.010)
H
W
K
Q_
For More Information On This Product, Go to: www.freescale.com
EE EE EE EE
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DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
MC68HC908GZ8 MOTOROLA
Freescale Semiconductor, Inc.
Ordering Information and Mechanical Specifications 48-Pin Low-Profile Quad Flat Pack (LQFP)
25.4 48-Pin Low-Profile Quad Flat Pack (LQFP)
4X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE AB IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS T, U, AND Z TO BE DETERMINED AT DATUM PLANE AB. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE AC. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE AB. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.350. 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.170 0.270 1.350 1.450 0.170 0.230 0.500 BSC 0.050 0.150 0.090 0.200 0.500 0.700 0x 7x 12 xREF 0.090 0.160 0.250 BSC 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF
0.200 AB T-U Z 9 A1
48 37
A
DETAIL Y
P
1
36
T B B1
12 25
U V AE V1 AE
Freescale Semiconductor, Inc...
13
24
Z S1 S
4X
T, U, Z DETAIL Y
0.200 AC T-U Z
AB
G
0.080 AC
AD AC
BASE METAL
DIM A A1 B B1 C D E F G H J K L M N P R S S1 V V1 W AA
M
TOP & BOTTOM
R
GAUGE PLANE
C F D 0.080
M
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AC T-U Z H W DETAIL AD AA K L
SECTION AE-AE
MC68HC908GZ8 MOTOROLA Ordering Information and Mechanical Specifications
0.250
N
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Data Sheet 341
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc.
Ordering Information and Mechanical Specifications
Freescale Semiconductor, Inc...
Data Sheet 342 Ordering Information and Mechanical Specifications
MC68HC908GZ8 MOTOROLA
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc.
HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan 81-3-3440-3569 ASIA/PACIFIC:
Freescale Semiconductor, Inc...
Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong 852-26668334 TECHNICAL INFORMATION CENTER: 1-800-521-6274 HOME PAGE: http://motorola.com/semiconductors
Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark Office. digital dna is a trademark of Motorola, Inc. All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
(c) Motorola, Inc. 2003
MC68HC908GZ8/D Rev. 0 2/2003
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